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# Design Engineer

- **Company:** Broadcom
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Salary:** $108,000.0 - $192,000.0
- **Contract:** Permanent contract
- **Skills:** Extract Transform Load (ETL), Software Debugging, Logic Synthesis of Circuits, Ethernet, PCI Express, Performance Tuning, SystemVerilog, Verilog, Low Latency
- **Published:** May 19, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=6a271eaceee812ef

## About the Role

* Expert-level SystemVerilog/Verilog for high-speed digital design.
 * Deep knowledge of PCIe and Ethernet and datapath optimization.
 * Practical experience with protocol analyzers and hardware-level debugging is a plus.
 * Bachelor's plus 8+ years OR Master's in Engineering plus 6+ years related industry experience.

## Description

Role Summary: Architecture and RTL implementation of high-speed datapaths and control logic. Focuses on high-throughput data movement and the integration of PCIe and Ethernet protocols with embedded micro-controllers.

Core Responsibilities:

 * Datapath Design: Architect and implement high-speed, low-latency datapaths and complex FSMs in (System)Verilog.
 * Protocol Integration: Lead the design and integration of PCIe and Ethernet sub-systems.
 * Controller Interfacing: Design interfaces between high-speed logic and embedded micro-controllers.
 * Hardware Debug: Perform hands-on debug and performance tuning of PCIe/Ethernet traffic.


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