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# RTL Design & Integration Engineer

- **Company:** Advanced Micro Devices, Inc.
- **Location:** San Jose, CA, United States
- **Salary:** $166,400.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Bash Shell, Software Quality, Computer Engineering, Software Debugging, Electronic Design Automation, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Python (Programming Language), Oracle Virtual Machine, Cadence Virtuoso, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Data Analytics, Vlsi Design, Physical Design
- **Published:** August 24, 2026
- **Apply:** https://diversityjobs.com/main/sendform/8/8/28176/1/18055543?backUrl=%2Fcareer%2F18055543%2FRtl-Design-Integration-Engineer-California-San-Jose

## About the Role

* Expertise in RTL design (Verilog/SystemVerilog), including digital/analog block implementation.
 * Understanding of VLSI design flow, from RTL through Physical Design and GDSII.
 * Familiarity with Physical Implementation processes: floorplanning, synthesis, P&R, STA.
 * Experience with EDA tools (Synopsys Design Compiler, Primetime, VCS; Cadence Virtuoso).
 * Knowledge of UVM/OVM verification, simulation environments, and debugging.
 * Understanding of FPGA architecture and usage models is a plus.
 * Proficiency in scripting (Perl, Tcl, Python, Shell) for design automation.
 * Excellent communication skills and ability to thrive in a fast-paced, global environment., * Bachelor's or Master's in Computer Engineering or Electrical Engineering.

## Description

As a key member of AMD's FPGA Product development team, you will have various responsibilities in the technical execution of Adaptive & Embedded Computing Group (AECG) device programs from conception & planning to productization. You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in supporting PPA, cost and schedule optimized Silicon implementation and first-time-right SW solution., * Collaborate with architects, hardware engineers, and SW-FW engineers to understand the product requirements and IP features.

 * Build early-stage RTL designs based on product and architecture intent driving Silicon and Solution co-development.

 * Build and enhance AI-driven infrastructure to accelerate IP integration and improve development timelines.
 * Apply data-driven methodologies to align engineering teams across next-generation products and technology nodes.
 * Support functional simulation and software quality checks, ensuring robust verification coverage.
 * Partner with global teams to achieve seamless integration and delivery., AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.


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