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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Quantum Systems Digital Design Engineer II - **Company:** Microsoft - **Location:** San Francisco, CA, United States - **Salary:** $102,100.0 - $202,200.0 - **Contract:** Permanent contract - **Skills:** Microsoft Windows, Artificial Intelligence, Microsoft Online Services, C++ (Programming Language), Code Review, Computer Engineering, Software Debugging, Linux, Ethernet, Firmware, Formal Verification, Field-Programmable Gate Array (FPGA), Hardware Design, Python (Programming Language), PCI Express, Azure DevOps Pipelines, Signal Processing, Verification and Validation (Software), Specman, Static Timing Analysis, Systems Architecture, System Testing, SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Git, Low Latency - **Published:** August 25, 2026 - **Apply:** https://www.dice.com/job-detail/0bad277a-dc87-4c87-850d-1b8f5a530840 ## About the Role * Master's Degree in Physics, Electrical/Computer Engineering, or related field AND 1+ years experience in industry or in a research and development environment + OR Bachelor's Degree in Physics, Electrical/Computer Engineering, or related field AND 2+ years experience in industry or in a research and development environment + OR equivalent experience. * This position requires verification of citizenship or other protected status to meet legal requirements of the role. If the role requires ship, as indicated in the job description, a valid US passport must be provided to verify your citizenship. Additional or Preferred Qualifications * 3+ years building production FPGA designs in Verilog/SystemVerilog (or VHDL), including synthesis, P&R, and static timing analysis on Xilinx/AMD (UltraScale+/Versal/RFSoC) and/or Intel platforms. * Proven delivery of low-latency, streaming datapaths (DSP, filtering, classification, or decoder-like pipelines) with tight timing closure at high clocks. * Hands-on with high-speed I/O and protocols: AXI4/AXIS, JESD204(B/C), Aurora, multi-gig SERDES; competent in link bring-up, eye margins, and error budget analysis. * Proficiency in clocking/CDC fundamentals and experience with multi-clock, multi-reset systems. * Verification skills (simulation, assertions, testbenches; UVM a plus) and lab debug using ILA/ChipScope, scopes, LA, and RF test gear. * Familiarity with RFSoC architectures (data converters, JESD links) and/or heterogeneous co-processing with CPGPUs. * Comfort working across HW/SW boundaries (DMA perf tuning, drivers, gRPC/REST control surfaces, telemetry/observability) and with scientific instrumentation. * Experience accelerating decoders (e.g., graph/union-find/MWPM-style or LDPC-class techniques), streaming inference/classification, or similar real-time algorithms. * Exposure to HLS (C/C++/HLS kernels) and mixed HLS/RTL systems; formal verification. * Background in signal processing/control or quantum control/readout concepts (nice to have; curiosity and fast learning are more important). * Experience with Windows & Linux, VS Code, Git/GitHub, Azure DevOps CI/CD; scripted builds (Tcl/Python); design docs + code reviews + comprehensive testing are part of our quality bar. Other Requirements * Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: * Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. * Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. * Ability to work in an "AI first" environment using modern AI tools to accelerate discovery through hardware development. * Familiarity with designing and building AI agents/copilots that assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval. ## Description * Design & implement RTL for streaming, low-latency pipelines (e.g., readout classifiers, syndrome aggregation, and QEC decoder kernels) in Verilog/SystemVerilog, including resource/performance trade-offs and power/thermal considerations. * Design and implement high-speed interconnects between subsystems (AXI4/AXI-Stream, JESD204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring-up, and throughput/latency tuning. * Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi-domain timing closure, async FIFOs, metastability analysis) for deterministic performance. * Co-design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams; contribute to system-level design reviews. * Verification and validation: develop simulation and constrained-random tests (SV/UVM or equivalent), build on-board diagnostics (ILA/ChipScope), and execute lab bring-up with scopes, VNAs, LA/SC, and RF instruments. * Tool flow & CI: own synthesis/implementation (Vivado/Vitis or QuartPrime), timing sign-off, and reproducible, scripted builds (Tcl/Python) integrated with Git/Azure DevOps CI/CD. * Quality & documentation: produce clear design docs, interface specs, and bring-up guides; participate in rigorous code/design reviews and post-silicon/post-fabrication retros. ## Related Videos - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [Quantum DevOps - Quantum Application Development](https://www.wearedevelopers.com/videos/1441-quantum-devops-quantum-application-development) - [Docker exec without Docker](https://www.wearedevelopers.com/videos/1094-docker-exec-without-docker) - [Git for Code Reviews](https://www.wearedevelopers.com/videos/429-git-for-code-reviews) - [Quantum Computing - The tiny and the big challenges](https://www.wearedevelopers.com/videos/934-quantum-computing-the-tiny-and-the-big-challenges) ## Related Articles - [7 Cloud Computing Trends Coming in 2025 for Developers](https://www.wearedevelopers.com/magazine/412-7-cloud-computing-trends-coming-in-2025-for-developers) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [The Fastest-Growing Tech Sectors to Look Out for in 2025](https://www.wearedevelopers.com/magazine/373-the-fastest-growing-tech-sectors-to-look-out-for-in-2025) - [Dev Digest 134 - Where pixels sing?](https://www.wearedevelopers.com/magazine/477-dev-digest-134-where-pixels-sing) - [How to Become an AI Engineer](https://www.wearedevelopers.com/magazine/331-how-to-become-an-ai-engineer) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated)