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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU - **Company:** Samsung - **Location:** San Jose, CA, United States - **Experience:** Expert - **Salary:** $219,000.0 - **Contract:** Temporary contract - **Skills:** Artificial Intelligence, C++ (Programming Language), Computer Programming, Computer Engineering, Microarchitecture, Data Centers, Microprocessors, High-Level Architecture, Python (Programming Language), Reduced Instruction Set Computing, Backend, Information Technology, Virtual Agents - **Published:** August 27, 2026 - **Apply:** https://diversityjobs.com/main/sendform/8/8/28176/1/18090187?backUrl=%2Fcareer%2F18090187%2FPrincipal-Engineer-Architecture-Performance-Research-Engineer-For-Data-Center-Agentic-Ai-Cpu-California-San-Jose ## About the Role * Master's degree in Computer Engineering, Computer Science, or a related field with 18+ years of relevant experience, or PhD with 15+ years of relevant experience * 8+ years of experience in CPU microarchitecture, architecture research, or performance engineering, with a demonstrated track record of driving architectural direction * Extensive experience designing and evaluating high-performance CPU architectures, including RISC-V, ARM, or x86 cores; experience with GPU/NPU vector or accelerator architectures is also relevant * Proven ability to use quantitative performance analysis and modeling to identify architectural opportunities, evaluate system-level trade-offs, and influence major microarchitectural decisions * Deep expertise in at least one major microarchitectural domain, with the ability to drive architectural direction and technical decisions in that area: * Front-end: Branch prediction, fetch/decode, instruction delivery, and decoupled front-end architectures * Mid-end: Out-of-order execution, scheduling, RVV/SIMD, vector execution, or matrix/tensor acceleration * Back-end: Load/store units, MSHRs, cache and memory systems, prefetching, or irregular memory access optimization Hands-on experience building, extending, and applying architectural simulators and performance models, such as gem5, to guide architecture decisions Strong programming skills in C/C++ and Python, with experience developing tools and automation for performance analysis and architectural exploration Demonstrated ability to take architectural concepts from research and modeling through RTL implementation and silicon validation, * Experience defining or influencing CPU architecture for emerging workloads, particularly AI/ML, agentic AI, or data center applications * Experience with AI-driven architecture and design methodologies, including AI-assisted architecture exploration, high-level design, or RTL generation * Strong perspective on memory-centric architectures and CPU-memory co-design, with experience translating memory-system characteristics into CPU architectural opportunities * Experience driving system-level PPA trade-offs across performance, power, area, and implementation complexity * Experience taking architectural concepts through RTL implementation, tape-out, and silicon validation * Experience leading cross-functional architecture initiatives and influencing technical direction across multiple engineering teams * Proven ability to mentor and develop senior technical engineers and shape architecture research across multiple domains * Track record of impactful architectural innovation through patents, publications, or deployed products * You're inclusive, adapting your style to the situation and diverse global norms of our people. * You approach challenges with curiosity and resilience, seeking data to help build understanding. * You're collaborative, building relationships, humbly offering support and openly welcoming approaches. * Innovative and creative, you proactively explore new ideas and adapt quickly to change ## Description As a Principal CPU Architecture & Performance Engineer, you will define the architectural vision and performance direction for next-generation CPU platforms. You will identify opportunities across emerging workloads, shape long-term architectural strategies, develop and refine performance models, and drive new microarchitectural concepts across multiple architectural domains. You will work closely with RTL design teams and cross-functional engineering partners to translate architectural vision into implementable designs, influence key technical decisions, and validate architectural choices from modeling through silicon. The role carries broad technical ownership, with the opportunity to establish new research directions, drive architecture across multiple generations of CPUs, and shape the fundamental design choices that determine future CPU performance and capabilities. * Define the application-specialization direction for next-generation CPU cores, including agentic AI and memory-centric architectures, and lead the overall microarchitectural vision * Lead end-to-end performance analysis using architectural simulators and RTL, guiding key architectural trade-offs and decisions * Translate workload characterization and performance insights into architectural requirements and long-term design direction * Drive architecture-to-implementation alignment with design teams, ensuring architectural intent is carried through RTL and silicon * Mentor Senior and Staff engineers and provide technical leadership across multiple projects and architectural domains * Drive research and technical contributions leading to patents and publications, At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision-maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically. ## Related Videos - [Developing the Backend with Stefan Lingler, CTO at Shpock](https://www.wearedevelopers.com/videos/100360-developing-the-backend-with-stefan-lingler-cto-at-shpock) - [The Sustainability Race: AI's Promises, Pitfalls and Potential](https://www.wearedevelopers.com/videos/100155-the-sustainability-race-ai-s-promises-pitfalls-and-potential) - [Guiding Agentic AI with Vue](https://www.wearedevelopers.com/videos/2033-guiding-agentic-ai-with-vue) - [Unleashing the Full Potential of the Arm Architecture – Write Once, Deploy Anywhere](https://www.wearedevelopers.com/videos/940-unleashing-the-full-potential-of-the-arm-architecture-write-once-deploy-anywhere) - [Building the Nervous System of AI - Michael Kagan (NVIDIA)](https://www.wearedevelopers.com/videos/2133-building-the-nervous-system-of-ai-michael-kagan-nvidia) - [AI Factories at Scale](https://www.wearedevelopers.com/videos/1139-ai-factories-at-scale) ## Related Articles - [How to Become an AI Engineer](https://www.wearedevelopers.com/magazine/331-how-to-become-an-ai-engineer) - [Stephan Gillich - Bringing AI Everywhere](https://www.wearedevelopers.com/magazine/489-stephan-gillich-bringing-ai-everywhere) - [Navigating the AI Shift](https://www.wearedevelopers.com/magazine/629-navigating-the-ai-shift) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [Got AI ideas but no money? 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