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# digital verification engineer

- **Company:** Ciena Limited
- **Location:** Bad Homburg vor der Hohe, Germany
- **Experience:** Experienced
- **Contract:** Permanent contract
- **Skills:** C (Programming Language), Systems Engineering, JIRA, Bash Shell, C++ (Programming Language), Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Ethernet, Formal Verification, Python (Programming Language), Object-Oriented Software Development, SystemVerilog, Software Verification, Git, Bug Reporting, Information Technology, Software Version Control, Programming Languages
- **Published:** August 28, 2026
- **Apply:** https://www.stepstone.de/stellenangebote--DSP-ASIC-Verification-Engineer-Optical-Transmission-Systems-Germany-Braunschweig-Ciena-Limited-German-Branch--13895817-inline.html

## About the Role

* Expert-level experience (3 years +) in digital design verification of complex circuits\n
 * Electrical or computer engineering, computer science or other applicable scientific degree at MEng/MSc level\n
 * Expertise in SV-UVM, SVA and C++ coding\n
 * Expertise in creating comprehensive verification plans from specifications\n
 * Expertise in building verification environments using SV-UVM and C++\n
 * Familiar with metric-driven verification methods including functional coverage\n
 * Familiar with EDA verification tools and flows from major vendors\n
 * A highly motivated self-starter, able to work independently, while being a great teammate\n
 * Ability to methodically solve complex technical problems\n
 * Excellent organization, written and oral (English) interpersonal skills.\n
 * Basic communication skills in German.\n, * Experience with formal verification methods\n
 * Experience with coherent DSP architectures\n
 * Experience with standards and protocols such as OTN/FlexO/B100G, Ethernet (100GE+)\n
 * Experience with using GIT for source code management and revision tracking\n
 * Experience with using Jira for schedule planning, assignment tracking and bug reporting\n
 * Familiarity with programming languages such as Python, Make, bash, object-oriented programming, C, C++\n

## Description

Your role as a digital verification engineer will be required to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products.
\n
\n

 * As a digital verification engineer you are required to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects\n
 * You will be held responsible for the complete and detailed validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods\n
 * You will contribute to verification planning, functional coverage definition and possibly formal verification test plans\n
 * You will be accountable for the creation or integration of the test bench components, agents, scoreboard, and test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable.\n
 * You will perform coverage-driven verification, monitor regressions and debug resulting failures with the help of the function's designer.\n
 * Reporting on status updates on a regular basis\n


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