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# Senior GPU Top Micro-Architect

- **Company:** Apple Inc.
- **Location:** London, UK
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Revision Control Systems, Python (Programming Language), Ruby, SystemVerilog, Tcl (Programming Language), VHSIC Hardware Description Language (VHDL), Scripting, Physical Design
- **Published:** August 28, 2026
- **Apply:** https://www.totaljobs.com/job/senior-architect/apple-job107903118

## About the Role

* Expertise in design including logic synthesis
 * Expertise in SystemVerilog/VHDL and proficiency in revision control systems
 * Strong problem-solving skills, ability to work across team boundaries and be productive under aggressive schedules, * Understanding of computer architecture and physical design
 * Experience with large-scale SoC or GPU design
 * Experience of scripting languages (for example Python/Ruby/Tcl)

## Description

The GPU top design team develops micro-architecture and RTL for critical top-level infrastructure IP, and drives micro-architectural improvements across the entire GPU through our holistic system-level perspective.We own complete IP blocks including interconnects, control logic, and clocking/reset distribution. Our unique position working across the full GPU scope enables us to identify optimization opportunities that span multiple units which means our micro-architecture work can influence outside of IP that we own when we identify better system-level solutions.We handle the complete design flow for our IP from concept through physical design handoff, while also contributing to GPU-level assembly and integration.

Responsibilities

 * Micro-architecture development (for owned IP and system-level improvements)
 * IP design and synthesis (owned blocks)
 * Design clocking and reset distribution, perform CDC/RDC verification
 * Contribute to GPU top-level assembly/integration
 * Debug and analyse top-level design issues
 * Prepare deliverables for physical design handoff
 * Codeline management, supporting multiple products & chips
 * Review RTL implementations and mentor junior engineers


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