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# Senior ASIC Timing Engineer

- **Company:** NVIDIA Corporation
- **Location:** Santa Clara, CA, United States
- **Experience:** Expert
- **Salary:** $136,000.0 - $218,500.0
- **Contract:** Permanent contract
- **Skills:** Boolean Algebra, Computer Engineering, Logic Synthesis of Circuits, Microprocessors, Routing, Static Timing Analysis, Graphics Processing Unit (GPU), Application Specific Integrated Circuits, Macros, Physical Design
- **Published:** August 28, 2026
- **Apply:** https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Timing-Engineer_JR2017336

## About the Role

* BS (or equivalent experience) in Electrical or Computer Engineering with 5 years' experience or MS (or equivalent experience) with 3 years' experience in Timing and STA
 * Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
 * Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
 * Experience in physical design and optimization e.g., synthesis, placement, routing, logic restructuring, etc. to improve timing and power.
 * Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
 * Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.

Ways to stand out from the crowd:

 * Background in domain specific STA and timing convergence, such as GPUs, CPUs, LPU or SOCs
 * Background in logic synthesis and equivalence checking/FV.
 * Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc.
 * Understanding and timing closure of digital logic/macros in AMS designs/IPs.
 * Experience in methodology and/or flow development as well as automation.

## Description

* Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level.
 * Collaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs.
 * Contribute to Cutting-Edge Projects: Play a pivotal role in the success of our innovative projects and advancement of our technology. Leverage your expertise to improve timing convergence flows in collaboration with methodology teams.


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