> Markdown version of [/jobs/ext/2279027-fpga-engineer](https://www.wearedevelopers.com/jobs/ext/2279027-fpga-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # FPGA Engineer - **Company:** Arrow Electronics - **Location:** San Jose, CA, United States - **Salary:** $125,000.0 - $165,000.0 - **Contract:** Permanent contract - **Skills:** Board Bringup, Adobe InDesign, Boolean Algebra, Software Debugging, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Hardware Description Language, PCI Express, Software Requirements Analysis, Static Timing Analysis, Subversion, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Git, Software Version Control - **Published:** August 28, 2026 - **Apply:** https://find.jobs/jobs-near-me/apply/ats-redirect/?id=2942801823-2 ## About the Role * FPGA design (Xilinx/AMD, Intel/Altera) * VHDL/Verilog/System * Verilog * Digital logic design and RTL coding * Simulation and verification (Model * Sim/Questa, Vivado, etc.) * Timing closure and static timing analysis * High-speed interfaces (PCIe, DDR, Ethernet, SERDES) * Embedded systems and So * C/So * C-FPGA integration * Schematic reading and hardware bring-up * Version control (Git, SVN) * Lab test and measurement (oscilloscopes, logic analyzers) ## Description Arrow Electronics is seeking an FPGA Engineer to design, implement, and verify high-performance FPGA solutions for advanced electronic systems within our Engineering & Design team. You will translate system requirements into HDL architectures, perform simulation and timing closure, and integrate FPGAs into complex hardware platforms. Collaborating with cross functional teams, you'll optimize performance, power, and reliability while following best in class design and verification practices. In our performance driven, innovative, and inclusive culture, you'll work with cutting edge tools and technologies, contribute to customer success, and grow your skills on impactful, global projects., * Design and implement FPGA architectures from system requirements using HDL (VHDL/Verilog/System * Verilog). * Develop, run, and debug simulations and testbenches to verify FPGA functionality and performance. * Perform timing closure, constraint development, and static timing analysis for reliable operation. * Integrate FPGA designs with boards, processors, and peripheral interfaces in complex electronic systems. * Collaborate with hardware, firmware, and software engineers to define requirements and system interfaces. * Optimize FPGA designs for performance, power consumption, and resource utilization. * Support board bring-up, lab testing, and failure analysis using test and measurement equipment. * Document designs, interfaces, and verification results following engineering best practices. * Participate in design reviews and contribute to continuous improvement of design and verification flows. * Stay current with FPGA tools, IP, and industry trends to recommend and adopt new solutions. ## Related Videos - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Git for Code Reviews](https://www.wearedevelopers.com/videos/429-git-for-code-reviews) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Unleashing the Full Potential of the Arm Architecture – Write Once, Deploy Anywhere](https://www.wearedevelopers.com/videos/940-unleashing-the-full-potential-of-the-arm-architecture-write-once-deploy-anywhere) - [Stop Committing Your Secrets - GIt Hooks To The Rescue!](https://www.wearedevelopers.com/videos/573-stop-committing-your-secrets-git-hooks-to-the-rescue) ## Related Articles - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Dev Digest 188: CfP time, the risks of NPM and IKEA algorithms](https://www.wearedevelopers.com/magazine/635-dev-digest-188-cfp-time-the-risks-of-npm-and-ikea-algorithms) - [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Dev Digest 130 - The Diablo is in the details](https://www.wearedevelopers.com/magazine/470-dev-digest-130-the-diablo-is-in-the-details) - [Dev Digest 125 - Duck and Cover](https://www.wearedevelopers.com/magazine/462-dev-digest-125-duck-and-cover)