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# Design Verification Architect

- **Company:** Intel Corporation
- **Location:** Santa Clara, CA, United States
- **Experience:** Expert
- **Salary:** $164,470.0 - $232,190.0
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Software Debugging, Digital Arts, SystemVerilog, Strategies of Testing, GitHub Copilot, Git, Infrastructure Automation Frameworks
- **Published:** August 28, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3367764938&tx=JT10395UTD&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Collaborative and communicative, with the ability to work across diverse teams and mentor junior engineers
 * Strong problem-solving skills with disciplined execution and a proactive mindset
 * Results-driven, with the ability to drive optimal solutions between analog and digital designs, Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates., Bachelor's degree with 10+ years of relevant industry experience, or a Master's degree in a related field with 8+ years of relevant industry experience

You must have 8+ years of experience with/in:

 * IP/SoC pre-silicon validation and coding using SystemVerilog
 * Hardware simulation tools and methodologies (VCS/Verdi)
 * IP environment and configuration management tools
 * UVM methodology, * Demonstrated ability to debug complex logic designs and validate system-level functionality
 * DDR design domain knowledge with strong understanding of DFI/DDR/LPDDR protocols
 * Experience with VSCode, GitHub Copilot, or any other AI-assisted development tools
 * Experience to Formal Property Verification and Git version control

## Description

Defines, architects, and documents verification strategy and methodologies for implementing and verifying the pre-silicon design in the most optimal manner. Architects testbenches and develops Universal Verification Methodology (UVM) or formal-based verification approaches. Integrates block testbenches in chip-level UVM environments and verifies integration., * Define, architect, and document verification strategy and methodologies for implementing and verifying pre-silicon design in the most optimal manner

 * Architect testbenches and develop Universal Verification Methodology (UVM) or formal-based verification approaches
 * Integrate block testbenches in chip-level UVM environments and verify integration
 * Develop test strategy, testbench architecture, and test plans for design blocks to conform to specifications
 * Enable interaction with analog and digital teams and support post-silicon validation activities
 * Collaborate with architecture and design teams to create random test generation plans, run functional simulations to identify gaps in design specifications, and conduct failure analysis, coverage analysis, and closure
 * Define and develop the security validation strategy and validation infrastructure to incorporate security tools and methods to improve security coverage, This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.


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