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# SoC Product Architect Low Power SoC

- **Company:** NVIDIA Corporation
- **Location:** Santa Clara, CA, United States
- **Experience:** Expert
- **Salary:** $224,000.0
- **Contract:** Permanent contract
- **Skills:** Apple IOS, Computer Engineering, ONNX (Open Neural Network Exchange) Format, TensorRT
- **Published:** August 28, 2026
- **Apply:** https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/SoC-Product-Architect-Low-Power-SoC_JR2014841

## About the Role

* 12+ years in SoC or product architecture, with deep hands-on knowledge of CPU, GPU, memory, and low-power IO subsystems
 * Master's Degree in Computer Engineering or Electrical Engineering (or equivalent experience)
 * Strong understanding of SoC architecture for low power mobile devices, including DVFS, power domains, and retention strategies
 * Experience with DL inference at the edge (TensorRT, TFLite, ONNX) and mapping workloads to constrained hardware
 * Track record of driving architecture decisions across multi-functional teams in a large organization

Join the future of chip building, you will contribute to innovative products with a dedicated team!

## Description

We are looking for a senior SoC/Product Architect to define and drive the architecture of next-generation low-power SoCs at NVIDIA. You will own concept-to-product architecture decisions - balancing power, performance, and area - while partnering across CPU, GPU, memory, and IO teams to resolve system-level trade-offs and acting as the technical interface for product requirements and customer feedback.

What you'll be doing:

 * Define SoC architecture for low-power platforms - CPU, GPU, memory subsystem, low-power IOs, and power management
 * Drive concept-level PPA trade-off analysis and lead the power/performance budget across the SoC
 * Architect the memory subsystem (LPDDR5/6, on-chip SRAM, bandwidth, QoS) for constrained power envelopes
 * Work with DL teams for evaluating and crafting workloads for low power - mapping tasks to constrained hardware; define optimization opportunities in partnership with Nvidia's DL team.
 * Partner with CPU, GPU, and IO architecture teams inside NVIDIA to align on shared IPs and integration strategies
 * Translate customer requirements into architectural constraints; drive PRD development and requirements triage
 * Engage directly with customers pre-silicon to collect feedback and follow through on product decisions


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