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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior SoC Subsystem and I/O Architect - LPU - **Company:** NVIDIA Corporation - **Location:** United States (Remote available) - **Experience:** Expert - **Salary:** $184,000.0 - $287,500.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Architectural Patterns, C++ (Programming Language), Computer Engineering, Microarchitecture, Software Debugging, Fault Tolerance, Firmware, High-Level Architecture, Python (Programming Language), PCI Express, Remote Access Service, Subsystems, SystemC, Strategies of Testing, Virtualization Technology, Deep Learning, Information Technology, Low Latency, U-Boot, Software Usability - **Published:** August 28, 2026 - **Apply:** https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Remote/Senior-SoC-Subsystem-and-I-O-Architect---LPU_JR2020327 ## About the Role * BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience. * 8+ years of proven experience in SoC architecture, subsystem architecture, IO architecture, interconnect architecture, GPU/CPU architecture, accelerator architecture, or high-performance systems. * Strong understanding of SoC architecture and uncore subsystem development. * Extensive understanding of IO and interconnect cores including PCIe, CXL, NVLink, NVLink-C2C, UCIe, AXI, CHI, or NoC fabrics. * Experience working from product requirements to architecture requirements and IP/subsystem specifications. * Experience crafting functional models, architectural models, golden models, or C/SystemC models from architecture specifications. * Solid grasp of memory ordering, coherency, address translation, interrupts, virtualization, MMUs/IOMMUs, enumeration, configuration, and error management. * Solid knowledge of boot, reset, firmware handoff, capability discovery, security, RAS, debug, and power-management architecture. * Strong communication abilities and capability to harmonize architecture decisions across IP, firmware, software, verification, and product groups. Ways To Stand Out from the crowd: * Hands-on experience with LPU, GPU, CPU, AI accelerator, chiplet, or multi-die SoC architecture. * Extensive knowledge in PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, coherent fabrics, NoCs, or chip-to-chip links. * Extensive knowledge in formulating architecture specifications for advanced SoC subsystems. * Experience building executable functional models directly from product, architecture, or protocol specs. * Understanding of deep learning workloads, numerics, memory architecture, and bandwidth/latency tradeoffs. * Experience with boot architecture, reset sequencing, secure boot, RAS, debug, DFT, power sequencing, or post-silicon validation. ## Description We are seeking a Senior SoC Subsystem & I/O Architect to join our ambitious LPU team. This role involves establishing the high-level architecture for next-generation AI and high-performance computing products. The role requires extensive architectural expertise across SoC subsystems and uncore IPs including PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, NoC fabrics, memory systems, coherency, boot, system initialization, protection mechanisms, reliability, availability, serviceability, power management, debug, firmware interfaces, and platform initialization. If you are prepared to make a difference and be part of a dedicated team, this is your opportunity! What You'll Be Doing: * Define high-level SoC subsystem architecture for LPU products. * Convert LPU product requirements into architectural specifications for uncore, IO, memory, firmware-facing, boot, reset, safety, fault tolerance, diagnostic, and power regulation subsystems. * Collaborate intimately with IP teams to develop detailed build documents for PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, NoC fabrics, memory controllers, coherency blocks, MMUs/IOMMUs, boot, reset, and associated SoC infrastructure. * Specify subsystem behavior encompassing enumeration, capability discovery, configuration flows, sequence control of memory operations, data consistency, address mapping, interrupt handling, virtualization, error handling, and firmware/software-visible controls. * Build or guide functional and architectural models from specifications, using C++, SystemC, Python, or similar languages. * Use models to validate architecture intent, subsystem behavior, configuration sequences, and IP interactions before RTL or silicon is available. * Drive tradeoffs across bandwidth, latency, power, area, timing, scalability, reliability, security, debuggability, and software usability. * Review IP specifications, subsystem architecture documents, model behavior, verification plans, and validation strategies. * Collaborate with architecture, IP, firmware, software, RTL, verification, platform, and post-silicon teams to bring architecture decisions to completion. ## Related Videos - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [Coffee with Developers - Stephen Jones - NVIDIA](https://www.wearedevelopers.com/videos/1303-coffee-with-developers-stephen-jones-nvidia) - [From Model to Metal: An Open Source Stack for Accelerating Intelligence](https://www.wearedevelopers.com/videos/1636-from-model-to-metal-an-open-source-stack-for-accelerating-intelligence) - [Agent Smith Gets Hardware: Autonomous IoT Hacking From Debug Port to Cloud API](https://www.wearedevelopers.com/videos/100258-agent-smith-gets-hardware-autonomous-iot-hacking-from-debug-port-to-cloud-api) - [Unleashing the Full Potential of the Arm Architecture – Write Once, Deploy Anywhere](https://www.wearedevelopers.com/videos/940-unleashing-the-full-potential-of-the-arm-architecture-write-once-deploy-anywhere) - [When Agents Meet Legacy: Never Change a Running System](https://www.wearedevelopers.com/videos/100320-when-agents-meet-legacy-never-change-a-running-system) ## Related Articles - [What Are Large Language Models?](https://www.wearedevelopers.com/magazine/304-what-are-large-language-models) - [Everything a Developer Needs to Know About MCP with Neo4j](https://www.wearedevelopers.com/magazine/604-everything-a-developer-needs-to-know-about-mcp-with-neo4j) - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [MLOps And AI Driven Development](https://www.wearedevelopers.com/magazine/82-mlops-and-ai-driven-development) - [MLOps – What’s the deal behind it?](https://www.wearedevelopers.com/magazine/125-mlops-what-s-the-deal-behind-it) - [Best US AI Conferences for CTOs in 2026: Build vs. Buy, Vendor Evaluation, and Peer Intelligence](https://www.wearedevelopers.com/magazine/736-best-us-ai-conferences-for-ctos-in-2026-build-vs-buy-vendor-evaluation-and-peer-intelligence)