> Markdown version of [/jobs/ext/2282110-principal-digital-design-engineer-chip-lead](https://www.wearedevelopers.com/jobs/ext/2282110-principal-digital-design-engineer-chip-lead). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Principal Digital Design Engineer / Chip Lead

- **Company:** Micron Technology, Inc.
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $178,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Application Integration Architecture, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Network Interface Controllers, Static Timing Analysis, SystemVerilog, Application Specific Integrated Circuits, Formal Methods, Physical Design
- **Published:** August 28, 2026
- **Apply:** https://www.sanjosejobsite.com/job.asp?id=3367764788&tx=JT10395UTD&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
 * 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or senior designer role
 * Expert-level proficiency in SystemVerilog RTL design and coding best practices
 * Strong experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus)
 * Proficiency with industry-standard RTL simulation and debug tools (VCS, Xcelium, or equivalent; Verdi or DVE for waveform debug)
 * Solid understanding of CDC analysis methodologies and tools (SpyGlass, JasperGold CDC, or equivalent)
 * Demonstrated experience integrating hard and soft IP blocks in a mixed-signal or PHY-adjacent chip environment
 * Ability to work effectively as a technical lead on a small team - comfortable making decisions with incomplete information and owning the outcomes
 * Strong written communication skills - this role produces specifications, not just code
 * Experience partnering with design verification teams to define verification plans, review coverage metrics, and drive closure of functional and corner-cases prior to tape-out.
 * It is expected that the candidate will be proficient in leveraging AI for productivity.

Preferred

 * Experience with high-speed PHY architectures (SerDes, DDR, or equivalent analog I/O structures)
 * Familiarity with I2C management bus architecture, Eye Monitor control logic, or PRBS-based error counting implementations
 * Experience with DFT strategy definition including scan insertion, ATPG planning, and boundary scan for high-speed I/O
 * Familiarity with OTP/fuse-based trim and calibration architectures for PHY analog parameters
 * Prior experience in a small team or startup-like environment where role boundaries are defined by need rather than org chart

## Description

* Chip Architecture & Integration: Define top-level chip architecture, partition responsibilities across hard and soft IP blocks, and own the integration of hard macros alongside third-party soft IP.
 * RTL Design: Author, review, and maintain synthesizable RTL (SystemVerilog) for all soft IP control blocks, CSR/register file, clocking control logic, and top-level integration.
 * Timing Closure Leadership: Develop and own chip-level timing constraints (SDC), define clock domain crossing strategy, and provide timing budgets per block to the Physical Design engineer.
 * Synthesis: Drive logic synthesis (DC / Genus) and guide optimization for PPA targets across all design blocks.
 * Verification Coordination: Partner with DV staff to apply assertion-based verification, coverage-driven verification, formal methods and constrained-random techniques to ensure high quality verification of control logic, interfaces, and system behaviors.
 * IP Management: Define interfaces between PHY hard macro, third-party soft IP, and internally designed blocks; manage IP integration agreements and vendor coordination.
 * Tape-Out Ownership: Own and drive the tape-out checklist sign-off process, coordinating across Physical Design, Verification, and analog team members to achieve clean handoff to the foundry.
 * Design Documentation: Author architecture specifications, block-level design specifications, and interface control documents that serve as the authoritative reference for the team.
 * Follow-On Roadmap: Capture design decisions, lessons learned, and architectural rationale to accelerate follow-on chip development., * You will have full technical ownership of a chip from day one - no waiting for a senior engineer to hand you a subsystem.
 * You will work alongside genuinely exceptional analog designers - including engineers with deep SerDes and clocking expertise - in an environment where analog and digital engineers work as genuine collaborators, not in silos.
 * The team is intentionally small and senior - decisions get made quickly, bureaucracy is minimal, and your judgment will be trusted.
 * You are joining an active program with real momentum - your technical leadership will directly shape its trajectory and scope going forward.


## Related Videos

- [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right)
- [When testing just doesn’t cut it](https://www.wearedevelopers.com/videos/720-when-testing-just-doesn-t-cut-it)
- [Building a fully automated escape room](https://www.wearedevelopers.com/videos/735-building-a-fully-automated-escape-room)
- [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age)
- [AI Meets Hoare Logic: Revolutionizing Software Testing with Formal Methods](https://www.wearedevelopers.com/videos/1644-ai-meets-hoare-logic-revolutionizing-software-testing-with-formal-methods)
- [Designing for Every Direction: Logical CSS for Global, Adaptive, and Effortlessly Reversible UIs](https://www.wearedevelopers.com/videos/2026-designing-for-every-direction-logical-css-for-global-adaptive-and-effortlessly-reversible-uis)

## Related Articles

- [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again)
- [What’s the Difference between a Junior, Mid, and Senior Developer?](https://www.wearedevelopers.com/magazine/238-what-s-the-difference-between-a-junior-mid-and-senior-developer)
- [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline)
- [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers)
- [Never delegate the understanding](https://www.wearedevelopers.com/magazine/749-never-delegate-the-understanding)
- [Dev Digest 132 - Binging WADFlix?](https://www.wearedevelopers.com/magazine/473-dev-digest-132-binging-wadflix)