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# Senior Deep Learning Hardware Modeling Architect - LPU

- **Company:** NVIDIA Corporation
- **Location:** United States (Remote available)
- **Experience:** Expert
- **Salary:** $152,000.0 - $241,500.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, C++ (Programming Language), Profiling, Software Tools, Large Language Models, Deep Learning, Parallel Computation
- **Published:** August 28, 2026
- **Apply:** https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Remote/Senior-Deep-Learning-Hardware-Modeling-Architect---LPU_JR2019216

## About the Role

* A BS or higher degree in a relevant field (CS, EE, Math) or equivalent experience, with 5+ years of relevant experience.
 * Expert programming and software skills in C++.
 * Experience in RTL design and/or architecture with the ability to understand common chip design concepts.
 * An automation-centered mindset.
 * A desire to improve work efficiency using AI.

Ways to stand out from the crowd:

 * Experience with systems-level/architectural/chip modeling, profiling, and analysis.
 * Strong combined RTL and C++ skillset.

## Description

NVIDIA seeks a Senior DL Hardware Modeling Architect to join our group of pioneers who are pushing the performance boundaries of AI inference. Our team focuses on ambitious hardware-software co-design to optimize AI inference speed and efficiency. This role gives an outstanding opportunity to model critical components of our world-class LLM inference solutions. If you are passionate about LLM inference hardware, want to contribute at the deepest levels to the state of the art, and have a proven record of C++ hardware modeling experience, this role may be perfect for you!

What you'll be doing:

 * Drive architectural specifications to closure across multiple stakeholders.
 * Develop written specifications for key component-level and system-level designs.
 * Embody specifications in an executable model used by many customers across NVIDIA.
 * Ensure high performance using good C++ software practices, solid algorithms and data structures, and parallelism.
 * Resolve performance and correctness issues across chip and hardware subsystems by working across teams.


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