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# Senior I/O Subsystem Architect

- **Company:** NVIDIA Corporation
- **Location:** Santa Clara, CA, United States
- **Experience:** Expert
- **Salary:** $224,000.0
- **Contract:** Permanent contract
- **Skills:** Data Link, Computer Engineering, Firmware, PCI Express, Subsystems, Systems Architecture, Information Technology
- **Published:** August 28, 2026
- **Apply:** https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-I-O-Subsystem-Architect_JR2012554

## About the Role

* MS or PhD in Electrical Engineering, Computer Science or Computer Engineering (or equivalent experience)
 * 10+ years of relevant experience in some combination of architecture, design, and verification
 * Proven experience over link layer architecture (Transaction layer, Data link layer, Physical layer)
 * Experience with existing interconnects (PCIE, UCIE, Chip to Chip links) and knowledge of Industry standard protocols CHI/CXL/AXI
 * Able to define system architecture with NVLINK-C2C interconnects and SW stack around it
 * Collaborate with multi-functional teams including IP, SoC, physical/package design, firmware, electrical design, and validation to drive interconnect technology development and integration
 * Evaluate and trade off technical solutions to meet platform requirements for current and future products
 * Have completed and shipped multiple projects and are skilled at I/O Architecture
Experience leading projects from concept through product lifecycle, including pathfinding, prototyping, and deployment

## Description

NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols. You'll be part of a team responsible for defining next generation communications standards and products building on our current NVLink technology. The job scope ranges from developing initial product requirements, working with research, other architects, software/firmware and product development teams to shepherd the design through all phases of the product lifecycle.

What you will be doing:

 * Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency
 * Working with other design teams to define interfaces and flows between NVLink C2C blocks and the rest of the chip
 * Architectural modeling, validation, definition and documentation
 * Driving implementation across design, verification, firmware and software teams
 * Working with various teams to define NVLink C2C architecture


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