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# Digital Verification Engineer

- **Company:** Photeon Solutions Gmbh
- **Location:** Dornbirn, Austria
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Code Coverage, Software Debugging, Formal Verification, Specman, SystemVerilog
- **Published:** August 29, 2026
- **Apply:** https://www.chancenland.at/jobposting/senior-digital-verification-engineer-f-m-d/

## About the Role

* Education or degree: Bachelor or Master degree or equivalent in electrical engineering or physics
 * Work experience: +5 years of professional experience in Digital Verification
 * Technical skills: Expertise in advanced verification methodologies, especially UVM. Experience designing and implementing testbench architectures. Strong proficiency with verification languages (e.g., SystemVerilog, Specman, 'e'). Familiarity with industry-standard CAD tools and verification flows.
 * Soft skills: Excellent teamwork and collaboration skills. Solid understanding of semiconductor physics and technology.
 * Good verbal and written English skills, German is an advantage

## Description

Mindestausbildung: Bachelor
Arbeitssprache:
Standort: Dornbirn
Kontaktperson: Johanna Ammann

Bewerbungen bitte per E-Mail
Stellenbeschreibung

As a market leader in turnkey solutions, Photeon offers the opportunity to work on a diverse range of products across Automotive, Compute, Industrial, Medical, and other markets. We are seeking a dynamic Senior Digital Verification Engineer to join our team and drive our projects to success. We provide an energetic, exciting, and friendly environment with numerous opportunities for your professional growth in the direction that suits you best.

We welcome you to become a key contributor to our success, fostering collaboration and teamwork every step of the way.

Your Role: The Senior Digital Verification Engineer is responsible for ensuring the functional correctness and quality of complex digital designs through the development and execution of comprehensive verification strategies. This role involves defining verification methodologies, creating testbenches, writing and running test cases, analyzing coverage, and debugging failures. The engineer collaborates closely with design, architecture, and system teams to validate that the design meets specifications and performance targets. Additionally, the role includes mentoring junior team members and driving continuous improvements in verification processes and tools.

Tasks & Responsibilities:

 * Lead the development of UVM-based verification environments.
 * Perform pre-silicon verification of digital and mixed-signal designs.
 * Create detailed verification plans in collaboration with design and systems teams.
 * Implement automated checks and maintain spec-to-coverage traceability.
 * Define and drive functional and code coverage closure.
 * Provide regular verification progress updates to stakeholders.
 * Collaborate with design and systems teams to resolve bugs.
 * Track bugs, functional coverage, and RTL code coverage.


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