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# ASIC Engineer

- **Company:** Cisco Systems, Inc.
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $155,000.0 - $222,600.0
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Computer Engineering, Software Debugging, Electronic Design Automation, Perl (Programming Language), Job Scheduling, Python (Programming Language), Unix Shell, Shell Script, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Application Specific Integrated Circuits, Physical Design
- **Published:** August 29, 2026
- **Apply:** https://jobs.localjobnetwork.com/apply/add/88169428/1

## About the Role

* Bachelor's degree in Electrical or Computer engineering and 5+ years of ASIC Design experience or Master's degree in Electrical or Computer Engineering and 3+ years of experience, or PhD + 0 years of experience.
 * Experience with Verilog/SystemVerilog programming.
 * Experience with interactive and waveform debugging.
 * Experience with industry-standard DFT/EDA tools and ability to work closely with design, verification, and test teams to resolve flow and methodology issues.
 * Scripting experience in Python, Perl, TCL, or shell programming.

Preferred Qualifications:

 * Experience with Synopsys Design Constraints (SDC).

## Description

* Develop, maintain, and enhance DFT CAD infrastructure and automation and Support DFT implementation flows like Scan insertion, ATPG generation, SPF generation, pattern simulation etc
 * Develop utilities and automation using Python, Perl, Tcl, and Shell scripting.
 * Debug DFT flow failures and work with design teams to resolve issues.
 * Create and maintain regression frameworks and dashboards.
 * Improve flow robustness, runtime, and scalability.
 * Support large-scale regressions on compute farms using LSF or equivalent job schedulers.
 * Develop documentation, FAQs, and onboarding material for internal users.
 * Support releases, tool qualification, and regression signoff.
 * Collaborate with DFT Design, ATPG, Verification, Physical Design, and CAD teams.


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