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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Sr. DFT Engineer, Amazon Leo - **Company:** Amazon.com, Inc. - **Location:** San Diego, CA, United States - **Experience:** Expert - **Salary:** $159,200.0 - $215,300.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Joint Test Action (IEEE Standards), Application Specific Integrated Circuits - **Published:** August 29, 2026 - **Apply:** https://www.amazon.jobs/en/jobs/10520541/sr-dft-engineer-amazon-leo ## About the Role Bachelor's degree in Electrical/Communications Engineering, or experience working in electrical engineering field - 5+ years of experience in advanced DFT techniques for deep sub-micron nodes. - Experience implementing DFT methodology and developing automated scripts for DFT Insertion and Validation., Master's or Ph.D degree in Electrical / Communications Engineering. - 7+ years of experience in DFT, including exposure to Logic BIST. - Familiarity working with RFIC engineers on chips that have a large Mixed signal component. - Experience with automotive standards and ways to achieve single digit DPPM targets. - Experience developing automation flow using AI/ML-based solutions to improve DFT implementation workflow. ## Description Be part of Amazon LEO's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: · Architect and define DFT solutions adapted to the specific use of various LEO's chips. · Contribute to the improvement and customization of IPs and DFT methodology while embracing AI flow. . Work with the ASIC design teams in all the sites to incorporate DFT logic like MBIST, clock controls and JTAG controllers. . Work with RFIC teams to ensure maximum fault coverage on the custom RF blocks. · Ensure that blocks meet DFT, timing and power targets by working closely with the implementation team. · Work closely with the Test engineering team to help translate the ATE patterns to tester format. · Work with the test team to do jointly bring up the digital portions of the LEO chips. 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