> Markdown version of [/jobs/ext/2297285-senior-implementation-engineer-amazon-leo](https://www.wearedevelopers.com/jobs/ext/2297285-senior-implementation-engineer-amazon-leo). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Implementation Engineer, Amazon Leo - **Company:** Amazon.com, Inc. - **Location:** San Diego, CA, United States - **Experience:** Expert - **Salary:** $159,200.0 - $215,300.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Databases, Application Specific Integrated Circuits, Physical Design - **Published:** August 29, 2026 - **Apply:** https://www.amazon.jobs/en/jobs/10520540/senior-implementation-engineer-amazon-leo ## About the Role Bachelor's degree in Electrical Engineering or a related field - 7+ years of experience in ASIC implementation, i.e., synthesis, STA and working with P&R for deep sub-micron nodes, preferably 16nm or smaller. - Experience leading or solely developing the methodology and scripts for physical synthesis. - Proven track record in taping out chips that have gone in to high volume production. - Familiar with implementing chips that have multiple power islands and power gating., Master's or Ph.D degree in Electrical / Communications Engineering. - 10+ years of experience in ASIC implementation. - Experience in leading physical design. - Strong exposure to UPF flow for low power design. - Strong written and verbal skills - Experience of working in multi-site/multi-team environment ## Description Be part of Amazon Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: * As the implementation lead you will work with the ASIC design team to develop the chip power intent using UPF * As the implementation lead you will work with the ASIC design team to validate UPF at RTL and netlist level using industry standard tools * As the implementation lead you will set up the flow for both logic and physical synthesis flow for various technology nodes. * Develop implementation methodologies while embracing AI flow. * Work with the ASIC design and DFT teams to understand the design and create timing constraints. * Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work with RFIC teams to make sure the top level integration of analog blocks are done properly and correct by construction, including formal connectivity checks. * Work with P&R teams to ensure a smooth hand off of netlists, ensure the timely execution of the P&R responsibilities by that team. * Participate in flow reviews of all the blocks with the P&R team to ensure that they achieve the best PPA for all blocks. * Lead the timing sign-off for the post P&R database. * Ensure that the chip meets the required DFM criteria by verifying the IR/EM results. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. ## Related Videos - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Kubernetes and Microservices with Multi-Model Databases](https://www.wearedevelopers.com/videos/382-kubernetes-and-microservices-with-multi-model-databases) - [Building a fully automated escape room](https://www.wearedevelopers.com/videos/735-building-a-fully-automated-escape-room) - [Edit Your Future: Queerverse Radical AI](https://www.wearedevelopers.com/videos/909-edit-your-future-queerverse-radical-ai) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [Fault Tolerance and Consistency at Scale: Harnessing the Power of Distributed SQL Databases](https://www.wearedevelopers.com/videos/1146-fault-tolerance-and-consistency-at-scale-harnessing-the-power-of-distributed-sql-databases) ## Related Articles - [How to Become an AI Engineer](https://www.wearedevelopers.com/magazine/331-how-to-become-an-ai-engineer) - [Stephan Gillich - Bringing AI Everywhere](https://www.wearedevelopers.com/magazine/489-stephan-gillich-bringing-ai-everywhere) - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Everything a Developer Needs to Know About MCP with Neo4j](https://www.wearedevelopers.com/magazine/604-everything-a-developer-needs-to-know-about-mcp-with-neo4j) - [Navigating the AI Shift](https://www.wearedevelopers.com/magazine/629-navigating-the-ai-shift) - [Graph and AI Trends 2026: Why Is AI Running but Not Yet Delivering?](https://www.wearedevelopers.com/magazine/680-graph-and-ai-trends-2026-why-is-ai-running-but-not-yet-delivering)