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# R&D IC Design Engineer

- **Company:** Broadcom
- **Location:** Irvine, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Unix, Computer Engineering, Software Debugging, Perl (Programming Language), Ethernet, Python (Programming Language), Software Requirements Analysis, Subsystems, Verilog, VHSIC Hardware Description Language (VHDL), Scripting, Application Specific Integrated Circuits
- **Published:** August 29, 2026
- **Apply:** https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-CA-Irvine-Alton-Parkway-Bldg-2/R-D-IC-Design-Engineer_R024630

## About the Role

* B.S degree in EE or computer Engineering. Minimum of 8 years of work experience with
direct related technical skill

 * M.S degree/Ph.D in EE or Computer Engineering with 6 years of work experience.
 * Good knowledge of ARM subsystem

 * Good knowledge of high speed digital circuit design.

 * Good knowledge of digital upsampling/downsampling

 * Good knowledge of 10G/100G/200G/400G/800G Ethernet and OTN network.
 * Good knowledge on FEC (Forward Error Correction) design.

 * Good knowledge of digital signal processing and error correction code is a plus

 * Strong analytical and problem solving skills as well as hands-on lab debugging
experiences

 * Good knowledge of RTL simulation and synthesis.

 * In-depth knowledge for design for low power and design for test and design for
manufacturing.

 * Good Knowledge in languages relevant to the ASIC development process including
Verilog, VHDL, Unix/Perl Scripting or Python, and C.

 * Self-motivated, excellent communication skills and ability to excel in a team
environment.

 * Good organization skills, able to follow through & bring issue to closure

 * Understand the entire IC development flow & procedure including silicon volume
production qualification requirements & procedures

 * Enthusiastic & enjoy IC development works

 * Be able to work with teams at remote locations with different time zone.

## Description

* This opening is for working on chips that enable Physical Layer Products for High
Speed Optical Communication.

 * architect block level design specifications from the marketing requirements and/or
system requirements

 * prepare detailed design document, timing constraint file

 * RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate level
simulations & silicon debug

 * Scripting for various IC design tasks such as STA, equivalency checks, test bench,
simulations, synthesis, etc.

 * prepare block level resource requirements & development schedule

 * generate verification & test plans for design validation

 * Perform design tradeoff analysis - leakage, dynamic power, die size, schedule, resource,
priority, etc.


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