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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Staff FPGA Digital Engineer - 5 - **Company:** Northrop Grumman - **Location:** Chandler, AZ, United States - **Salary:** $108,200.0 - $162,400.0 - **Contract:** Permanent contract - **Skills:** C++ (Programming Language), Computer Engineering, Software Debugging, Embedded C, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Hardware Description Language, Open Source Technology, PCI Express, Systems Development Life Cycle, Signal Integrity, Static Timing Analysis, System on a Chip, Systems Integration, Universal Asynchronous Receiver/Transmitter, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, ModelSim, Hardware Debugging - **Published:** August 30, 2026 - **Apply:** https://www.clearancejobs.com/jobs/9129182/staff-fpga-digital-engineer-5 ## About the Role * Bachelor's degree in Electrical Engineering, Computer Engineering , or related discipline from an accredited university and 12 years of relevant experience; or a Master's degree and 10 years of experience; or a PhD and 8 year s of experience. * Ability to obtain a U.S. Government Department of Defense (DoD) Secret security clearance at the time of application. * Advanced background i n FPGA/SoC design, with mastery in complex firmware development using VHDL (preferred) or Verilog . * Extensive experience with AMD Xilinx FPGAs and SoCs , with proficiency in managing design constraints (timing, power, I/O) and performing static timing analysis to achieve critical performance targets . * Advanced proficiency in development, verification, and debugging of MOSA interfaces/buses (Ethernet, PCIe , AXI4, UART, and SDLC) * Mastery with simulation tools (Questa / ModelSim ) and hardware debugging tools (logic analyzers, oscilloscopes). * Strong experience c reating and executing verification plans using simulation, analysis, and hardware bench test ing . * Deep knowledge of Open Source VHDL Verification Methodology (OSVVM) or Universal Verification Methodology (UVM). OSVVM preferred Preferred Qualifications : * MS or PhD in Electrical Engin eering, Computer Engineering, or related discipline. * Active U.S. Government DoD Secret security clearance at the time of application. * Experience with missile systems, seeker systems, or other high reliability, environmentally challenging electro optical applications. * Pr ior experience with DoD missile defense programs and associated standards. * Direct e xperience with AMD Xilinx Versal Gen 2 or Gen 1 * Mastery with both Vivado IDE and Vitis Unified IDE . * Advanced expe rience designing, integrating, and verifying DDR memory interfaces (e.g., DDR3/DDR4/DDR5) with fabric-based controllers in FPGA designs . * Deep u nderstanding of embedded C/C++ programming for integration with processors/SoCs . * Knowledge of high-speed PCB design and signal integrity . * Strong experience with OSVVM or UVM . ## Description As a Staff FPGA design engineer, you will apply advanced understanding and wide application of FPGA engineering principles, including mastery of methods and tools available for solving complex technical challenges. You will work closely with senior staff , ju nior staff , and cross-disciplinary teams (hardware, algorithms, and software) to p rovide technical solutions to a wide range of complex problems. The ideal candidate excels in fast-paced, collaborative environments and is comfortable managing multiple diverse assignments., * Lead resolution of design and integration challenges, drawing on advanced technical knowledge and wide application across disciplines. * Develop and execute high-level test benches to verify FPGA designs for functional correctness and timing requirements, managing configuration of multiple FPGA bitstream builds. * Generate, verify, and integrate IO and image processing HDL modules, including functions definitions, HDL coding, module-level simulation, and integration with device architecture. * Ensure compliance with internal design standards throughout the development lifecycle and mentor less experienced engineers. * Prepare, present, and maintain comprehensive design documentation including schematics, simulation results, and verification reports. * Stay abreast of evolving FPGA technologies, tools, and industry methodologies, demonstrating mastery in methods and tools available for addressing technical issues. ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) - [Security Pitfalls for Software Engineers](https://www.wearedevelopers.com/videos/726-security-pitfalls-for-software-engineers) ## Related Articles - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Top 6 Hackathons for Developers in 2023](https://www.wearedevelopers.com/magazine/263-top-6-hackathons-for-developers-in-2023) - [How Much FAANG Companies Actually Pay Software Engineers in 2025](https://www.wearedevelopers.com/magazine/230-how-much-faang-companies-actually-pay-software-engineers-in-2025) - [What’s the Difference between a Junior, Mid, and Senior Developer?](https://www.wearedevelopers.com/magazine/238-what-s-the-difference-between-a-junior-mid-and-senior-developer) - [9 Ways to Make Money Hacking](https://www.wearedevelopers.com/magazine/333-9-ways-to-make-money-hacking) - [Where to Find Entry-Level Software Engineering Jobs](https://www.wearedevelopers.com/magazine/397-where-to-find-entry-level-software-engineering-jobs)