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# CPU Design Timing Engineer

- **Company:** Apple Inc.
- **Location:** Austin, TX, United States
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Microprocessors, Perl (Programming Language), Python (Programming Language), CPU Design, Static Timing Analysis, Tcl (Programming Language), Physical Design
- **Published:** August 30, 2026
- **Apply:** https://www.austinjobsite.com/job.asp?id=3369814005&tx=FJ4542FFF&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Minimum BS required
 * Experience with script writing in one or more of the following languages: TCL, Perl, Python, * Implementation experience on high performance CPU designs
 * Working knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs
 * Good understanding of physical design tools and methodology including but not limited to physically aware synthesis and place & route tools and flows, extraction, and other analysis flows, and physical design verification (LEC, DVS, etc.)
 * Experience working on timing for 1 ghz+ designs, including how to handle multiple clock and power domains
 * Experience with one of the following static timing tools: Primetime or Tempus
 * Experience with cross talk, noise, OCV, uncertainty, and derate methodology

## Description

In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with constructing and modify timing flows, timing analysis, and timing closure., As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to:

 * Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency
 * Working extensively with CPU micro-architects and implementation engineers to drive timing closure for the CPU


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