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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Debug/Trace/Profiling Design Engineer - **Company:** SiFive Inc - **Location:** Cambridge, UK - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Confluence, JIRA, Boolean Algebra, Profiling, Microarchitecture, Software Debugging, Hardware Design, Joint Test Action (IEEE Standards), Object-Oriented Software Development, Reduced Instruction Set Computing, System on a Chip, SystemVerilog, Verilog, VHSIC Hardware Description Language (VHDL), Git, Functional Programming - **Published:** August 30, 2026 - **Apply:** https://www.collegerecruiter.com/job/2815593945-debugtraceprofiling-design-engineer ## About the Role * Knowledgeable in debug, trace and profiling architecture and concepts. * Knowledgeable in debug interfaces, JTAG and cJTAG. * Knowledgeable in CPU architectures, power management and SoC design. * Experience with debugging tools and profiling methods. * Proficiency with hardware (RTL) design in Verilog, System Verilog or VHDL. * Attention to detail and a focus on high-quality design. * Ability to work well with others and a belief that engineering is a team sport. * Knowledge of at least one object-oriented and/or functional programming language. * Knowledge of Chisel/Scala, RISC-V architecture, Git/Jira/Confluence is a plus. * 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high-performance processors. * MS or PhD in EE, CE, CS or a related technical discipline. ## Description SiFive is seeking a hardware design engineer passionate about designing industry-leading debug, trace and profiling IP to support the widespread adoption of RISC-V as the architecture of choice for SOC designs. The engineer will lead enhancements of existing debug/trace/profiling hardware and develop new capabilities, collaborating with customers, partners, tools vendors and the RISC-V International Association., The focus of this position is on debug, trace, and profiling hardware. The successful applicant will address the following challenges: * Design the best debug, trace and profiling hardware for open RISC-V and TileLink architectures. * Master designing hardware as configurable generators in a domain-specific software language for elaborating digital logic. * Work in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance., * Architect, design and implement debug, trace and profiling hardware. * Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification. * Implement RTL generators so elements self-configure to achieve extensive configurability as a first-class consideration. * Integrate new design content into SiFive's Chisel/FIRRTL framework and contribute to improvements that enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software. * Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans. * Ensure knowledge is shared via creation and maintenance of great documentation and participation in a collaborative design culture. ## Related Videos - [Talk to the Duck - Secrets of the Debugging Masters](https://www.wearedevelopers.com/videos/470-talk-to-the-duck-secrets-of-the-debugging-masters) - [Improving quality with Agentic AI with Rovo Dev and Xray](https://www.wearedevelopers.com/videos/2005-improving-quality-with-agentic-ai-with-rovo-dev-and-xray) - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [Debugging in the Dark](https://www.wearedevelopers.com/videos/1658-debugging-in-the-dark) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Collaboration Quantified: Lessons from Open Source Developer Networks](https://www.wearedevelopers.com/videos/1422-collaboration-quantified-lessons-from-open-source-developer-networks) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Software Engineer Career: Things You Should Know](https://www.wearedevelopers.com/magazine/143-software-engineer-career-things-you-should-know) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [The Best X (Twitter) Accounts for Developers](https://www.wearedevelopers.com/magazine/294-the-best-x-twitter-accounts-for-developers) - [Top Characteristics of a Software Engineer](https://www.wearedevelopers.com/magazine/166-top-characteristics-of-a-software-engineer)