> Markdown version of [/jobs/ext/2312475-fpga-engineer](https://www.wearedevelopers.com/jobs/ext/2312475-fpga-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# FPGA Engineer

- **Company:** Indotronix Avani Group
- **Location:** Fullerton, CA, United States
- **Experience:** Expert
- **Contract:** Temporary to permanent
- **Skills:** Unix, C++ (Programming Language), Computer Engineering, Digital Architecture, Digital Technology, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Global Positioning Systems (GPS), Signal Processing, SystemVerilog, VHSIC Hardware Description Language (VHDL), Scripting, Application Specific Integrated Circuits, ModelSim
- **Published:** August 30, 2026
- **Apply:** https://www.disabledperson.com/jobs/74632773-fpga-engineer

## About the Role

Active Secret clearance at start.

 - Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.

 - Expertise in FPGA design and/or verification.

 - Strong VHDL experience.

 - Proficiency with Intel/Altera FPGA tools (preferred), Modelsim, Synopsys, and/or FPGA vendor toolchains.

 - Experience with high?speed digital systems, interfaces, and signal processing.

 - Ability to work independently and communicate clearly in documentation and presentations.

 - Strong hands?on lab experience (non?negotiable)

Desired Skills:

 - SystemVerilog + UVM verification

 - ASIC experience (nice-to-have)

 - Design-for-Test (DFT) and manufacturability knowledge

 - Unix/Linux, scripting, C/C++, or Perl experience.

## Description

FPGA & ASIC Design Solutions team supporting next?generation military GPS and high?reliability digital systems. We are seeking experienced and motivated Senior Electrical or Computer Engineers with strong FPGA/ASIC design or verification backgrounds to contribute across requirements capture, digital architecture, RTL design, verification, and lab integration.


## Related Videos

- [WeAreDevelopers LIVE - Node and Package Security](https://www.wearedevelopers.com/videos/2138-wearedevelopers-live-node-and-package-security)
- [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips)
- [JavaScript? No. Java Scripts! - Scripting with Java](https://www.wearedevelopers.com/videos/2094-javascript-no-java-scripts-scripting-with-java)
- [Intermediate Bitcoin Script](https://www.wearedevelopers.com/videos/25-intermediate-bitcoin-script)
- [The Time Paradox: Building Timezone-Safe Python/Django Applications](https://www.wearedevelopers.com/videos/1915-the-time-paradox-building-timezone-safe-python-django-applications)
- [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right)

## Related Articles

- [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again)
- [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline)
- [Dev Digest 134 - Where pixels sing?](https://www.wearedevelopers.com/magazine/477-dev-digest-134-where-pixels-sing)
- [Should senior developers refuse interview coding challenges?](https://www.wearedevelopers.com/magazine/29-should-senior-developers-refuse-interview-coding-challenges)
- [Dev Digest 188: CfP time, the risks of NPM and IKEA algorithms](https://www.wearedevelopers.com/magazine/635-dev-digest-188-cfp-time-the-risks-of-npm-and-ikea-algorithms)
- [How software is steering vehicle technology](https://www.wearedevelopers.com/magazine/515-how-software-is-steering-vehicle-technology)