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# Senior RTL Design Engineer - PCIe Subsystems

- **Company:** Arm Limited
- **Location:** Cambridge, UK
- **Experience:** Expert
- **Salary:** £97,300.0 - £131,700.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Software Debugging, Electronic Design Automation, PCI Express, Software Tools, Subsystems, Systems Architecture, SystemVerilog, Systems Integration, Verilog, Scripting, GitHub Copilot, Front End Software Development
- **Published:** August 5, 2026
- **Apply:** https://jobs.theguardian.com/job/10166583/senior-rtl-design-engineer-pcie-subsystems/

## About the Role

* Hands-on working knowledge of SystemVerilog or Verilog HDL for RTL design
 * Solid understanding of RTL design techniques for complex SoC development
 * Familiarity with industry-standard EDA tools and methodologies
 * Experience in the following areas: static design checks, power and clock domain crossing, synthesis, timing constrains and SDCs
 * Understanding of the fundamentals of computer architecture and systems and practical experience of working on processor-based system designs

 * Knowledge of AI-powered software development tools and scripting workflows, including AI coding assistants such as Codex, GitHub Copilot, or equivalent technologies.

 * Good communication skills and ability to write specifications and documentation describing complex designs

Nice to Have Skills and Experience

 * Experience with Arm-based SoC designs, Arm system architectures, and AMBA protocols.
 * Knowledge of PCI Express (PCIe) and Compute Express Link (CXL) protocols.
 * Familiarity with low-power RTL design methodologies and analysis tools, including UPF/CPF, power and clock gating, state retention, and Dynamic Voltage and Frequency Scaling (DVFS).
 * Experience in setting up design flows and methodologies for large-scale SoC or subsystem development.

## Description

As a member of the Front-End Design team, you will contribute to the development of tape-out-ready PCIe subsystems for next-generation infrastructure SoCs. You will be responsible for planning your work, tracking progress, and reporting status to ensure the timely delivery of high-quality designs.

Your key responsibilities will include developing micro-architectures from high-level specifications, RTL design, coding and integrating a range of IPs, including Analog/mixed-signal IPs, PHYs, PLLs, Sensors and other subsystem components. You will perform comprehensive design quality checks, including Lint, CDC, RDC and other sign-off activities.

You will also collaborate closely with the verification team to review test plans, debug design issues, and ensure thorough functional coverage. In addition, you will work with the implementation team to review timing constraints and exceptions, define design partitions, and support engineering change orders (ECOs) through to tape-out.


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