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# Senior Silicon Design Verification Engineer, YouTube Video Accelerators

- **Company:** LOON LLC
- **Location:** Mountain View, CA, United States
- **Experience:** Expert
- **Salary:** $163,000.0 - $236,000.0
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Data Compression, Computer Engineering, Software Debugging, Electronic Design Automation, H.264/MPEG-4 AVC, SystemVerilog, Video Editing, Vivado, Information Technology
- **Published:** August 6, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=0ee08eaae93b69f2

## About the Role

* Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
 * 8 years of experience with Design Verification.
 * Experience with SystemVerilog and Universal Verification Methodology (UVM)., * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
 * Practical experience with High-Level Synthesis tools (e.g., Catapult, Vivado, XLS) and strong C/C++ skills for developing HLS testbenches and models.
 * Expertise in video processing, image pipelines, or video compression standards such as AV1, AV2, or H.264.
 * Demonstrated ability to debug complex issues across C/C++ and RTL levels using industry-standard EDA tools like VCS, Xcelium, or Verdi.

## Description

* Lead comprehensive verification strategies and signoff for complex blocks where the source is C/C++, taking full ownership of quality from HLS code to generated RTL.
 * Design and maintain advanced environments, including C/C++ GoogleTest for functional validation and SystemVerilog/UVM for RTL timing and system interactions.
 * Employ HLS-specific methods such as C/RTL co-simulation, formal equivalence verification, and transaction-level modeling to ensure hardware fidelity.
 * Drive complex bug hunting and coverage analysis across both C++ and RTL domains to ensure complete verification of the design transformation.
 * Partner with design teams to optimize C++ code for verifiability and mentor junior engineers on the nuances of HLS verification.


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