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# Digital and Mixed Signal IC Design/DV Engineer

- **Company:** Texas Instruments
- **Location:** Tucson, AZ, United States
- **Experience:** Experienced
- **Contract:** Permanent contract
- **Skills:** Boolean Algebra, Static Timing Analysis, SystemVerilog, Verilog, VHSIC Hardware Description Language (VHDL), Physical Design
- **Published:** August 6, 2026
- **Apply:** https://us.experteer.com/career/view-jobs/digital-and-mixed-signal-ic-design-dv-engineer-tucson-az-usa-58855194

## About the Role

* Contribute to evolution of DV strategy, tools, scripts, and methodologies to improve quality and automation Tasks * At least 2 years of relevant experience * Strong understanding of digital logic design * Familiarity with Verilog, SystemVerilog, and VHDL and simulators * Ability to solve problems using a systematic approach Key requirements * competitive pay and benefits * well-being focus and country-specific benefits * opportunity to shape future electronics

## Description

Experteer Overview In this role you contribute to the full IC development lifecycle for current sensing ICs, spanning architectural work, RTL design, DV, and bring-up. You work across digital and mixed-signal domains to drive first-pass silicon success and continuous DV improvements. You will collaborate with design and system teams to shape verification strategies and automation, delivering robust, scalable solutions. This is a hands-on opportunity to influence analog/digital mixed-signal challenges in a leading semiconductor environment. Compensation / Benefits * RTL design, synthesis, place and route, scan pattern generation, timing analysis * Develop verification methodologies for mixed-signal ICs; build testbenches and automation * Create test plans and simulations at RTL and gate levels using SV, VHDL, and UVM * Collaborate with design and system teams to define DFV architectures and triage bugs * Drive verification coverage, track progress, and report status, risks, and issues * Contribute to evolution of DV strategy, tools, scripts, and methodologies to improve quality and automation Tasks * At least 2 years of relevant experience * Strong understanding of digital logic design * Familiarity with Verilog, SystemVerilog, and VHDL and simulators * Ability to solve problems using a systematic approach Key requirements * competitive pay and benefits * well-being focus and country-specific benefits * opportunity to shape future electronics


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