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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Implementation Engineer, Amazon Leo - **Company:** Amazon.com, Inc. - **Location:** Sunnyvale, CA, United States - **Experience:** Expert - **Salary:** $159,200.0 - $215,300.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Databases, Application Specific Integrated Circuits, Physical Design - **Published:** August 31, 2026 - **Apply:** https://dejobs.org/x/x/5B992A8CC0484AAC8E61F67AD44B0493/job/ ## About the Role * Bachelor's degree in Electrical Engineering or a related field * 7+ years of experience in ASIC implementation, i.e., synthesis, STA and working with P&R for deep sub-micron nodes, preferably 16nm or smaller. * Experience leading or solely developing the methodology and scripts for physical synthesis. * Proven track record in taping out chips that have gone in to high volume production. * Familiar with implementing chips that have multiple power islands and power gating., * Master's or Ph.D degree in Electrical / Communications Engineering. * 10+ years of experience in ASIC implementation. * Experience in leading physical design. * Strong exposure to UPF flow for low power design. * Strong written and verbal skills * Experience of working in multi-site/multi-team environment ## Description Be part of Amazon Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: * As the implementation lead you will work with the ASIC design team to develop the chip power intent using UPF * As the implementation lead you will work with the ASIC design team to validate UPF at RTL and netlist level using industry standard tools * As the implementation lead you will set up the flow for both logic and physical synthesis flow for various technology nodes. * Develop implementation methodologies while embracing AI flow. * Work with the ASIC design and DFT teams to understand the design and create timing constraints. * Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work with RFIC teams to make sure the top level integration of analog blocks are done properly and correct by construction, including formal connectivity checks. * Work with P&R teams to ensure a smooth hand off of netlists, ensure the timely execution of the P&R responsibilities by that team. * Participate in flow reviews of all the blocks with the P&R team to ensure that they achieve the best PPA for all blocks. * Lead the timing sign-off for the post P&R database. * Ensure that the chip meets the required DFM criteria by verifying the IR/EM results. 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