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# HW Security Design Engineer

- **Company:** Qualcomm
- **Location:** San Diego, CA, United States (Remote available)
- **Experience:** Experienced
- **Salary:** $164,000.0 - $246,000.0
- **Contract:** Permanent contract
- **Skills:** Very-Large-Scale Integration, Boolean Algebra, Microarchitecture, Digital Arts, Federal Information Processing Standards (FIPS), Application Specific Integrated Circuits
- **Published:** May 22, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=5fad462a61da114f

## About the Role

Do you have experience in Technical writing within technology?, * 10+ years of experience with digital logic design and uArchitecture definition

 * Hands-on experience with VLSI/ASIC design and implementation
 * Familiarity with AHB, AXI, or APB protocols
 * Experience with technical document creation and maintenance for digital designs

Preferred Qualifications

 * In-depth knowledge of AES/SHA algorithms and modes and key handling principles
 * Experience with FIPS or Common Criteria certification
 * Experience implementing AHB/AXI/APB protocols
 * Experience with high-throughput architectures for cryptographic processing, * Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience., Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

## Description

* Work with architects to comprehend and interpret high-level specifications related to internal QCOM security IPs
 * Define and describe appropriate micro-architectures to meet the high-level specifications and deliver a micro-architecture document according to a defined schedule
 * Communicate with design and DV representatives to vet the document quality and useability
 * Be ready to implement (design/code) the design yourself, if needed
 * Follow IP updates and chip schedules to perform effort planning


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