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# RTL Design Engineer in Austin

- **Company:** Energy Jobline
- **Location:** Austin, TX, United States
- **Experience:** Starter
- **Salary:** $120,000.0 - $225,000.0
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Artificial Intelligence, Computer Engineering, Microarchitecture, Emulators, Data Flow Control, Static Timing Analysis, SystemVerilog, Verilog, Caching, Information Technology, Code Inspection, Hardware Acceleration, Physical Design
- **Published:** August 4, 2026
- **Apply:** https://www.energyjobline.com/job/rtl-design-engineer-austin-31347398

## About the Role

* Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.
 * 3+ years of industry experience in RTL design, microarchitecture, and architecture development.
 * Solid understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies).
 * Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines.
 * Familiarity with timing constraints, physical design considerations, and EDA flows.
 * Hands-on experience with simulation, synthesis, linting, and static timing analysis tools.
 * Strong problem-solving and communication skills with ability to work in cross-functional teams.

## Description

markets. The salary range for this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. RTL Design at Mythic:At Mythic, our RTL design team is at the heart of transforming our custom dataflow architecture into working silicon. RTL engineers take ownership of microarchitecture and RTL implementation, designing high-performance, low-power logic that enables our breakthrough AI hardware. The team works closely with architecture, custom analog IP, compiler, verification, emulation, and post-silicon teams to ensure every component integrates seamlessly into the full system. Because modern AI workloads push the limits of performance, memory, and efficiency, our RTL engineers apply creativity and rigor to deliver designs that meet aggressive PPA (performance, power, area) goals while ensuring correctness. We welcome engineers at all levels who are excited to tackle challenging design problems and play a key role in building the
next of AI compute hardware.Responsibilities

 * Design and implement RTL for Mythic's next- AI processor.
 * Develop and optimize high-performance, low-power components including datapaths, controllers, memory subsystems, and interconnects.
 * Collaborate with architects and verification engineers to define microarchitecture and ensure functional correctness.
 * Drive timing closure by working with synthesis and physical design teams.
 * Participate in design reviews and contribute to improving RTL coding practices and methodologies.


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