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# Software R&D Engineer, Digital Logic Synthesis - New College Grad 2026

- **Company:** NVIDIA Ltd.
- **Location:** Austin, TX, United States
- **Experience:** Starter
- **Salary:** $116,000.0 - $218,500.0
- **Contract:** Permanent contract
- **Skills:** Very-Large-Scale Integration, Boolean Algebra, Profiling, Data Structures, Logic Synthesis of Circuits, Distributed Systems, Machine Learning, Performance Tuning, Software Engineering, Static Timing Analysis, SystemVerilog, Verilog, Multithreading, Concurrency, Information Technology, C++14
- **Published:** May 16, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=b584026aabef0f32

## About the Role

Do you have experience in SoC?, * MS or PhD in Electrical Engineering or Computer Science (or equivalent experience).

 * Experience with EDA software and/or VLSI flows with focus in logic synthesis or digital optimization.
 * Strong CS fundamentals and modern C++ experience (templates/STL, concurrency libraries, profiling and performance optimization, data structures, algorithms, performance, concurrency, testing).
 * Solid understanding of RTL (Verilog/SystemVerilog) and digital design concepts (timing, clocking, DFT basics, power intent).
 * Experience in EDA techniques, including logic synthesis, global route, static timing analysis, power & area optimization and SAT solvers.

Ways to stand out from the crowd:

 * Previous experience involving RTL logic synthesis and multi stage logic optimization is a plus.
 * Experience with common EDA building blocks, such as Verific for Verilog parsing, Espresso for logic minimization, and various other components for logic rewriting, tree coverage, SAT solvers, and combinatorial optimization.
 * Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.
 * Experience with various machine learning techniques.

## Description

* Invent and develop new algorithms for RTL synthesis, digital logic optimization, graph-based RTL traversal, analysis, and manipulation.
 * Build physical-aware synthesis techniques using placement/congestion/timing feedback to improve PPA.
 * Develop strategies for rapidly analyzing the RTL change impact on timing, power, area, and impact to DFT, clocking, and power delivery on design.
 * Prototype and evaluate ML methods (e.g., GNNs, RL, models) to guide optimization decisions; integrate successful approaches into production.
 * Explore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis, especially that efficiently incorporate human insight.
 * As a team, own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.


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