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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # IO and Memory Sub-Sytem Architecture Organization - **Company:** Rambus Inc. - **Location:** San Jose, CA, United States (Remote available) - **Experience:** Expert - **Salary:** $180,000.0 - $334,200.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Dynamic Random-Access Memory, Firmware, Systems Analysis, Internet Protocol, Interoperability, Performance Tuning, Requirements Management, Signal Integrity, Subsystems, Systems Architecture, Systems Integration, Computer Network Operations, Application Specific Integrated Circuits, Server Operating Systems & Platforms - **Published:** August 11, 2026 - **Apply:** https://www.careerbuilder.com/job-details/io-and-memory-sub-sytem-architecture-san-jose-ca--86c8e0a6-c73b-42d4-811c-7d4b4d5f30d5 ## About the Role * Master's Degree (M.S.) in Electrical Engineering, Computer Engineering, or a related technical discipline. Experience * 12+ years of industry experience in semiconductor, ASIC, memory, or high-speed interface development. * Demonstrated experience leading complex technical projects and influencing architectural decisions. Key Competencies * System Architecture Leadership * DDR5/DDR6/LPDDR5/HBM Memory Expertise * High-Speed PHY Design * Tx/Rx Circuit Architecture * DFE/CTLE Equalization Techniques * I2C, I3C, USB Interfaces * Digital Design & Verification * Technical Specification Development * Analytical Problem Solving * Executive-Level Presentations, ASIC (Application Specific Integrated Circuit), Analysis Skills, Architectural Design, Architectural Services, Artificial Intelligence (AI), Computer Engineering, Computer Firmware, Cross-Functional, DRAM, Debugging Skills, Design Verification, Ecosystems, Electrical Engineering, Equalization, Genetics, Graphic Design, I2C, IP (Internet Protocol), Industry Standards, Interoperability, Interoperability Requirements, Joint Electron Device Engineering Council (JEDEC), Leadership, Memory Hardware, Memory Subsystem, Network Operations Center, PHY, Performance Analysis, Performance Management, Performance Tuning/Optimization, Problem Solving Skills, Product Development, RTL Design, Receivers, Requirements Management, Root Cause Analysis, Semiconductors, Signal Integrity, System Architecture, System Integration (SI), Systems Analysis, Technical Leadership, Technical Presentation, Technical Writing, Technical/Engineering Design, USB ## Description As a Senior Principal Architect of Memory & IO Sub-system, you'll play a pivotal role in leading the architecture, design, and development of next generation of DRAM sub-system solutions for server and high-performance computing applications. In this full-time role, you'll report directly to our VP of Engineering. Our Memory Interface Division is dedicated to developing all products related to Server and Client Memory Modules, and your contributions will be instrumental in developing solutions DDR6/LPDDR6/HBM solutions for Server and Client systems. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities: Lechnical Leadership * Lead the architecture, design, and development of next generation of memory subsystem solutions. * Drive technical decisions related to memory interfaces, PHY architecture, signal & power integrity, and system integration. * Define subsystem requirements and translate system-level needs into architecture and design specifications. * Provide technical leadership across multidisciplinary teams including ASIC, PHY, firmware, validation, system architecture, and platform engineering. Memory Subsystem Development * Develop expertise-driven solutions involving: * DDR4/5/6, LPDDR4/5/6, HBM3/4/5 DRAM * DDR4/5/6 Registered Clock Driver (RCD) * DDR4/5/6 Data Buffer (DB) * DDR4/5/6 DIMMs (RDIMM/LRDIMM/MRDIMM) * DDR4/5/6 Server Platforms * Analyze memory subsystem performance, timing, power, and interoperability requirements. * Drive systems bring-up, debug, characterization, and performance optimization activities. PHY Architecture and Design * Define and review high-speed PHY architectures for next-generation memory and interface products. * Develop and optimize: * Transmitter (Tx) architectures * Receiver (Rx) architectures * Clocking and timing circuits * Equalization schemes including DFE, CTLE, and related signal-conditioning techniques * Evaluate signal integrity challenges and develop solutions to improve channel performance and margin. Digital Design and Verification * Contribute to digital design, architecture reviews, and RTL implementation strategies. * Define verification methodologies and coverage requirements. * Lead debugging and root-cause analysis of complex design and system-level issues. * Collaborate with validation teams to ensure robust product functionality and compliance. Specification and Customer Engagement * Develop and maintain architecture specifications, design requirements, and technical documentation. * Present technical proposals, design reviews, and architecture recommendations to engineering leadership, customers, and ecosystem partners. * Translate JEDEC and industry standards into product requirements and implementation guidelines. * Participate in customer discussions, technical reviews, and interoperability initiatives. ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [10M Data Records Lost, Underwater Computing, and Psychedelic Fish - Matthias Geniar](https://www.wearedevelopers.com/videos/1908-10m-data-records-lost-underwater-computing-and-psychedelic-fish-matthias-geniar) - [Data Science in Retail](https://www.wearedevelopers.com/videos/586-data-science-in-retail) - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Unleashing the Full Potential of the Arm Architecture – Write Once, Deploy Anywhere](https://www.wearedevelopers.com/videos/940-unleashing-the-full-potential-of-the-arm-architecture-write-once-deploy-anywhere) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Everything a Developer Needs to Know About MCP with Neo4j](https://www.wearedevelopers.com/magazine/604-everything-a-developer-needs-to-know-about-mcp-with-neo4j) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline)