> Markdown version of [/jobs/ext/2481340-entry-level-asic-fpga-verification-engineer-space-electronics](https://www.wearedevelopers.com/jobs/ext/2481340-entry-level-asic-fpga-verification-engineer-space-electronics). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Entry Level ASIC/FPGA Verification Engineer - Space Electronics - **Company:** Boeing Company - **Location:** Mountain View, CA, United States - **Experience:** Starter - **Salary:** $79,050.0 - $106,950.0 - **Contract:** Internship / Graduate position - **Skills:** Code Coverage, Computer Engineering, Microarchitecture, Perl (Programming Language), Ethernet, Field-Programmable Gate Array (FPGA), Revision Control Systems, Hardware Description Language, Hardware Design, Python (Programming Language), Linux System Administration, Object-Oriented Software Development, PCI Express, Software Requirements Analysis, Static Timing Analysis, Subversion, SystemVerilog, Verilog, VHSIC Hardware Description Language (VHDL), Scripting, Application Specific Integrated Circuits, Git, Information Technology, Physical Design - **Published:** August 27, 2026 - **Apply:** https://www.clearancejobs.com/jobs/9127150/entry-level-asicfpga-verification-engineer-space-electronics ## About the Role * This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required. * Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement * Coursework, Projects, or internship experience with ASIC/FPGA verification * Familiarity with Register Transfer Language - e.g. Verilog, VHDL, SystemVerilog Preferred Qualifications (Desired Skills/Experience): * Bachelor's Degree in Electrical Engineering or Computer Engineering * Experience with hardware emulators, especially Palladium * Proficiency with hardware verification languages: System Verilog, System Verilog Assertions * Ability to executable test plans * Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc. * Ability to create self-checking and reusable testbenches from scratch * Experience developing Functional Coverage Models and Closing Code Coverage * Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet) * Proficient in scripting languages: Make, Perl, Python, etc. * Revision Control Systems: svn, cvs, git * Proficient in Linux Environments * Familiarity with space-based design techniques and radiation mitigation * Demonstrated history of 1st pass success with ASIC designs Conflict of Interest: Successful candidate for this job must satisfy the Company's Conflict of Interest (COI) assessment process. Typical Education/Experience: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics, or chemistry (e.g. Bachelor), or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard., This position must meet U.S. export control compliance requirements. To meet U.S. export control compliance requirements, a "U.S. Person" as defined by 22 C.F.R. ยง120.62 is required. "U.S. Person" includes U.S. Citizen, U.S. National, lawful permanent resident, refugee, or asylee., Bachelor's Degree or Equivalent Required, This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post-Start is required. ## Description * Develop FPGA/ASIC designs supporting design and/or verification teams * Implement FPGA/ASIC with latest design practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) * Integrate DSP IP from Boeing's algorithm team and third-party IP as needed * Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensure the design is completed on schedule * Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation * Create self-checking and reusable test benches from scratch, applying Object Oriented Programming concepts such as Inheritance and Polymorphism, and leverage UVM to build agents consisting of drivers, sequencers, monitors, and use of predictors together with scoreboards for checking correctness. * Support FPGA-based prototyping and validation depending on program and system requirements and complexity * Validate design through hardware integration test with special test equipment, test-beds, and higher-level systems as needed ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) ## Related Articles - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Where to Find Entry-Level Software Engineering Jobs](https://www.wearedevelopers.com/magazine/397-where-to-find-entry-level-software-engineering-jobs) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [Dev Digest 134 - Where pixels sing?](https://www.wearedevelopers.com/magazine/477-dev-digest-134-where-pixels-sing) - [How Much FAANG Companies Actually Pay Software Engineers in 2025](https://www.wearedevelopers.com/magazine/230-how-much-faang-companies-actually-pay-software-engineers-in-2025) - [Highest Paying Tech Companies in Europe](https://www.wearedevelopers.com/magazine/162-highest-paying-tech-companies-in-europe)