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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Semiconductor Design Engineer (Compute Test, Oregon) - **Company:** Teradyne Inc. - **Location:** Tualatin, OR, United States - **Experience:** Expert - **Salary:** $154,900.0 - $247,800.0 - **Contract:** Permanent contract - **Skills:** C (Programming Language), Microsoft Windows, JIRA, Boolean Algebra, C++ (Programming Language), IBM Rational ClearCase, Code Coverage, Continuous Integration, Software Debugging, Linux, Programming Tools, Logic Synthesis of Circuits, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Hardware Design, Python (Programming Language), PCI Express, Signal Integrity, Static Timing Analysis, Subversion, SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Scripting, Application Specific Integrated Circuits, Git, Physical Design - **Published:** August 20, 2026 - **Apply:** https://dejobs.org/x/x/F4EFFFE6285C433989F8530E3A9F06F1/job/ ## About the Role * BS in Electrical Engineering or a related field required; advanced degree preferred. * Minimum of 10 years of practical hardware development experience. * Primary experience in digital logic design and FPGA physical design, including floor-planning, place and route, and static timing analysis. * Expertise with Verilog and a scripting language such as Python, TCL, or PERL. * Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred. * Familiarity with SystemVerilog, UVM, VHDL, C, and C++ preferred. * Working knowledge of PCIe, AXI, DDRx, SERDES, USB, I2C, SPI, 10/100GE, PLL, HBM, DLL, ADC, DAC, MIPI, DisplayPort, and PRBS technologies. * Experience with Windows and Linux operating systems, as well as development tools including Cadence Xcelium, Synopsys SpyGlass CDC/LINT, Xilinx Vivado, Intel Quartus, ClearCase, Git, SVN, JIRA, and continuous integration methodologies. * Understanding of design for high-speed signal integrity. * Excellent troubleshooting, debugging, and problem-solving skills. * Strong verbal, written, and presentation skills. * Experience working in cross-functional teams designing complex systems. * Commitment to excellence, efficiency, mentorship, and product quality. ## Description The Semiconductor Design Engineer will play a key role within Teradyne's Compute Test Division Engineering team, focusing on the development of advanced test instrumentation. This role supports architecture, design, implementation, verification, and lab validation in a dynamic, multi-site engineering environment. The ideal candidate will bring strong digital logic design expertise, hands-on FPGA experience, and the ability to collaborate across hardware, software, systems, and verification teams. * Lead architecture, design, implementation, verification, and lab validation for test instruments and systems. * Develop scalable, high-performance, high-quality, extensible, and maintainable digital design solutions. * Collaborate with hardware, software, systems, and design verification teams to define requirements and achieve appropriate test coverage. * Build and execute product integration, verification testing, debug, prototyping, and characterization experiments. * Mentor junior engineers and provide technical leadership for FPGA project teams. * Support logic design process improvement initiatives and tool evaluations to sustain engineering excellence and product quality. All About You We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position. ## Related Videos - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [Improving quality with Agentic AI with Rovo Dev and Xray](https://www.wearedevelopers.com/videos/2005-improving-quality-with-agentic-ai-with-rovo-dev-and-xray) - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Git for Code Reviews](https://www.wearedevelopers.com/videos/429-git-for-code-reviews) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Is Software Engineering Hard?](https://www.wearedevelopers.com/magazine/448-is-software-engineering-hard) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers)