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# ASIC/FPGA Methodology Engineer (TERADYNE, North Reading, MA)

- **Company:** Universal Robotics Inc.
- **Location:** North Reading, MA, United States
- **Experience:** Experienced
- **Contract:** Permanent contract
- **Skills:** IBM Rational ClearCase, Computer Engineering, Continuous Integration, Software Debugging, Linux, Logic Synthesis of Circuits, Field-Programmable Gate Array (FPGA), Hardware Design, Static Timing Analysis, SystemVerilog, Systems Integration, Verilog, Vivado, Application Specific Integrated Circuits, Git, Docker, Jenkins, Hardware Debugging, Artifactory
- **Published:** August 7, 2026
- **Apply:** https://us.experteer.com/career/view-jobs/asic-fpga-methodology-engineer-teradyne-north-reading-ma-north-reading-ma-usa-58830515

## About the Role

_ support workflows * Provide technical guidance and training on FPGA/ASIC methodologies * Stay updated on industry trends to improve design methodologies Tasks * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field * 3+ years in FPGA and embedded design * Strong understanding of FPGA and embedded design principles * Hands-on experience with Vivado and Quartus * Familiarity with ASIC design flows and methodologies * Proficiency with Git, Docker, LSF, Jenkins, Artifactory, Clearcase * Knowledge of CI/CD workflows and automation tools * Understanding of SystemVerilog and UVM for digital design verification * Experience with timing analysis, synthesis, and timing closure * Familiarity with system-level integration and validation * Strong problem-solving and debugging skills Key requirements * medical, dental, vision * Flexible Spending Accounts * retirement savings plans * life and disability insurance * paid vacation & holidays * tuition a
workflows

## Description

Experteer Overview As an ASIC/FPGA Methodology Engineer, you define and maintain methodologies for FPGA/ASIC design and verification in a Linux-based environment. You will collaborate with design and verification teams to streamline workflows and optimize RTL/debug processes. You drive design flow improvements for FPGA tools and implement CI/CD pipelines, while guiding teammates on best practices. This role supports cutting-edge hardware development aligned with Teradyne's mission to enable reliable product manufacturing at scale. Compensation / Benefits * Develop and maintain ASIC/FPGA design, verification, and implementation methodologies * Collaborate with design and verification teams to integrate workflows and tools * Support RTL design work using Verilog and assist in debugging hardware issues * Optimize FPGA design flows for tools like Vivado, Quartus * Implement and manage CI/CD pipelines using Jenkins, Docker, and Git * Utilize Linux utilities (Git, Docker, LSF, Clearcase) to support workflows * Provide technical guidance and training on FPGA/ASIC methodologies * Stay updated on industry trends to improve design methodologies Tasks * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field * 3+ years in FPGA and embedded design * Strong understanding of FPGA and embedded design principles * Hands-on experience with Vivado and Quartus * Familiarity with ASIC design flows and methodologies * Proficiency with Git, Docker, LSF, Jenkins, Artifactory, Clearcase * Knowledge of CI/CD workflows and automation tools * Understanding of SystemVerilog and UVM for digital design verification * Experience with timing analysis, synthesis, and timing closure * Familiarity with system-level integration and validation * Strong problem-solving and debugging skills Key requirements * medical, dental, vision * Flexible Spending Accounts * retirement savings plans * life and disability insurance * paid vacation & holidays * tuition assistance


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