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# Lead Humanoid Robotics System Architect

- **Company:** Intel Corporation
- **Location:** Phoenix, AZ, United States
- **Experience:** Expert
- **Salary:** $220,920.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Distributed Systems, EtherCAT, Firmware, Machine Learning, Cyber-physical Systems, Systems Architecture, Information Technology, Low Latency
- **Published:** August 31, 2026
- **Apply:** https://www.phoenixjobs.com/job.asp?id=3370733704&tx=YT808CYV&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Core Experience: 10+ years in complex cyber-physical systems, with 4-5 years specializing in robotics, autonomous systems, or high-performance edge AI platforms.
 * BS in Engineering, Computer Science, Math, or related field is required.

Preferred Assets: Direct experience with humanoid robots/mobile manipulators, hands-on exposure to VLA/foundation models (-series, Helix-class, GR00T, OpenVLA, or equivalent), expertise with robotics platforms (NVIDIA Jetson / IGX platforms, custom AI silicon, or both), and battery/thermal budgeting for highly constrained systems.

## Description

This role serves as the authoritative systems architect owning the end-to-end hierarchical stack for next-generation humanoid robots. Acting as the critical interface between large-scale vision-language-action (VLA) models and physical platforms, this senior leader defines hierarchical multi-system architecture requirements and drives the co-optimization of advanced AI models with physical hardware under tight power, thermal, latency, and memory-bandwidth constraints., * Humanoid Robotic System Architecture Ownership: Own the canonical hierarchical control stack, including VLM/VLA systems, visuomotor policies, whole-body control, and distributed joint FOC loops. You will also establish rate boundaries, latency budgets, action-chunking strategies, and select interconnect topologies (e.g., EtherCAT).

 * AI Model Optimization for Silicon: Drive co-optimization of large VLA/world models with compute silicon. Define quantization, sparsity/MoE, context lengths, and reference deployment envelopes to align model workloads with silicon capabilities.
 * Co-Optimized Model + Hardware Architecture: Perform first-principles sizing of FLOPs, sustained TOPS, and memory-bandwidth floors. Select optimal compute platforms and design strategic splits of AI workloads between central compute nodes and remote sensor pods.
 * Key Deliverables with Cross-Functional Impact
 * Technical Leadership and Specifications: Author and maintain primary system-level specifications (compute, power, thermal, sensors, actuator networks, safety islands) and translate high-level product goals into actionable, quantitative requirements. Guide evolution of relevant technology roadmaps from current baselines to future system concepts that would influence product definition.
 * Cross-Functional Authority: Lead multi-disciplinary architecture reviews, key decisions, and subsystem design trades across ML research, controls, electrical, firmware, and mechanical teams.
 * Collaborative Experimentation and Mentorship: Formulate and guide expert-led viability experiments. Mentor senior engineers in system-level thinking, addressing critical hardware barriers like the memory and power walls, and represent the platform architecture with key external silicon and actuator partners.
 * Architectural Expertise: Proven ownership of architectures bridging high-level AI models with real-time hardware control, alongside deep fluency in transformer inference constraints (quantization, action chunking, memory bandwidth walls) and real-time distributed systems (EtherCAT, zonal sensor pods, safety islands).
 * Exceptional technical communication with a track record of writing rigorous, quantitative system specs and driving alignment across diverse engineering domains., This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.


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