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# VP of Systems Engineering

- **Company:** Lever, Inc.
- **Location:** Palo Alto, CA, United States
- **Salary:** $250,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Systems Engineering, Data Centers, Software Debugging, Firmware, PCI Express
- **Published:** August 6, 2026
- **Apply:** https://jobs.lever.co/mythic-ai.com/9368d3b2-34cb-48ba-8556-7e2b06ab193f/apply

## About the Role

* Excellent technical grounding in the hardware/software boundary, board-level electrical debug, and reasoning about the compiler/firmware stack that sits on top of custom silicon.
 * Proven track record building and scaling a systems or validation organization at a semiconductor or systems company.
 * Experience supporting external customers or OEM partners through technical qualification and deployment of new silicon.
 * Comfort operating in a startup environment - this role has less infrastructure and more ambiguity than the equivalent function at a large chip company, and requires building processes rather than inheriting them.
 * Preferred experience with novel or non-standard compute architectures (analog, in-memory, or otherwise non-GPU AI accelerators).
 * Preferred background at a large-scale systems engineering organization (e.g., NVIDIA, AMD, Qualcomm) in a bring-up/validation/platform role, with the judgment to know what to bring from that world and what to leave behind at Mythic's scale.
 * Preferred familiarity with edge AI deployment environments - robotics, automotive, or defense - where power, size, and reliability constraints are as important as raw performance.

## Description

* Own end-to-end systems engineering for Mythic's AMP-based products: post-silicon bring-up, platform/board-level validation, and characterization across the M1076 APU, PCIe cards, and M.2 modules.
 * Build and scale the systems engineering team as Mythic grows from single-chip products to multi-card and rack-scale deployments.
 * Drive hardware/software co-validation with firmware, compiler, and applications teams to ensure silicon performance claims (throughput, power, latency) hold up in real customer workloads.
 * Serve as the primary technical escalation point for silicon and platform issues raised by customers and partners across robotics, automotive, defense, and data center.
 * Own test infrastructure, automation, and characterization methodology to shorten the bring-up-to-production timeline for new silicon and card revisions.
 * Feed field and validation learnings back into next-generation chip and system design with product and architecture teams.


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