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# Principal FPGA Digital Engineer - 3

- **Company:** Northrop Grumman
- **Location:** Chandler, AZ, United States
- **Salary:** $108,200.0 - $162,400.0
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Configuration Management, Computer Engineering, Extract Transform Load (ETL), Software Debugging, Embedded C, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Hardware Description Language, Hardware Design, Open Source Technology, PCI Express, Systems Development Life Cycle, Signal Integrity, Static Timing Analysis, System on a Chip, Systems Integration, Universal Asynchronous Receiver/Transmitter, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, ModelSim, Hardware Debugging
- **Published:** August 1, 2026
- **Apply:** https://dejobs.org/x/x/D3E3459495EA4024B8DB4F8ED85BF9E3/job/

## About the Role

* Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline from an accredited university and 5 years of relevant experience; or a Master's degree and 3 years of experience; or a PhD and 1 year of experience.
 * Ability to obtain a U.S. Government Department of Defense (DoD) Secret security clearance at the time of application.
 * Solid background in FPGA/SoC design, including complex firmware development using VHDL (preferred) or Verilog.
 * Significant experience with AMD Xilinx FPGAs and SoCs.
 * Knowledgeable in managing design constraints (timing, power, I/O) and performing static timing analysis to achieve critical performance targets using Vivado IDE;
 * Proficient in development, verification, and debugging of MOSA interfaces/buses (Ethernet, PCIe, AXI4, UART, and SDLC)
 * Competency with simulation tools (Questa/ModelSim) and hardware debugging tools (logic analyzers, oscilloscopes).
 * Creating and executing verification plans using simulation, analysis, and hardware bench testing.
 * Understanding of Open Source VHDL Verification Methodology (OSVVM) or Universal Verification Methodology (UVM). OSVVM preferred, * MS or PhD in Electrical Engineering, Computer Engineering, or related discipline.
 * Active U.S. Government DoD Secret security clearance at the time of application.
 * Experience with missile systems, seeker systems, or other high reliability, environmentally challenging electro optical applications.
 * Previous experience or knowledge of DoD missile defense programs and associated standards.
 * Direct experience with AMD Xilinx Versal Gen 2 or Gen 1
 * Advanced experience with both Vivado IDE and Vitis Unified IDE.
 * Experience designing, integrating, and verifying DDR memory interfaces (e.g., DDR3/DDR4/DDR5) and fabric-based controllers (such as AXI or custom interconnects) in FPGA designs, including expertise in IP configuration, timing closure, signal integrity, and high-throughput data movement.
 * Understanding of embedded C/C++ programming for integration with processors/SoCs
 * Knowledge of high-speed PCB design and signal integrity
 * Strong experience with OSVVM or UVM.

## Description

As a principal FPGA design engineer, you will work closely with senior FPGA engineers and cross-disciplinary teams (hardware, algorithms, and software) to address design challenges and ensure seamless hardware integration. This role will focus on developing and executing test benches to independently validate FPGA designs for functional correctness and timing requirements, while adhering to internal design standards. The ideal candidate excels in fast-paced, collaborative environments and is comfortable managing multiple diverse assignments., * Collaborate with senior FPGA engineers and multidisciplinary teams (hardware, algorithms, software) to resolve design and integration challenges

 * Develop and execute advanced test benches to verify that FPGA designs meet functional and timing requirements
 * Generate, verify & integrate IO and image processing HDL modules. including functions definitions, HDL coding, module level sim and integration with overall device architecture
 * Ensure compliance with internal design standards throughout the development lifecycle
 * Oversee configuration management of multiple FPGA bitstream build configurations to support varied use cases or platform requirements
 * Prepare, present, and maintain comprehensive design documentation, including schematics, simulation results, and verification reports
 * Continuously expand technical knowledge by staying abreast of evolving FPGA technologies, tools, and industry methodologies


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