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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Staff Embedded Firmware Engineer, High Speed DSP - **Company:** Google LLC - **Location:** Sunnyvale, CA, United States - **Experience:** Expert - **Salary:** $192,000.0 - $278,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Bioinformatics, Bit Error Rate, C++ (Programming Language), Computer Networks, Computer Engineering, Data Recovery, Embedded Software, Firmware, Monitoring of Systems, Real-Time Operating Systems, AI Infrastructure, High Performance Computing, Bare Metal - **Published:** August 14, 2026 - **Apply:** https://www.techcareers.com/job.asp?id=3353277646&tx=YT1616THI&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54 ## About the Role Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain., * Bachelor's degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience. * 10 years of industry experience in embedded systems/firmware, communication systems engineering, or digital signal processing (DSP) development. * Experience developing embedded software (C/C++) for high-speed physical-layer interfaces (PHY), digital transceivers, or communication subsystems., * Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field. * Expertise in Forward Error Correction (FEC) algorithms and advanced modulation schemes. * Track record defining firmware framework specifications, register maps, and Silicon Lifecycle Management telemetry for high-volume networking or AI silicon. * Background in wireless communications with deep domain knowledge of channel modeling, noise mitigation, and digital transceiver architectures. ## Description * Define the long-term firmware roadmap and hardware-software partitioning for physical-layer interfaces, determining the optimal balance between hardware-fixed logic and programmable firmwarm. * Architect advanced "in-situ" monitoring systems and firmware-driven diagnostics to track physical-layer link health, Bit Error Rate (BER) trends, and channel quality across millions of ports in real-time. * Design, model, and implement bare-metal or RTOS firmware to control high-speed transceivers, managing real-time adaptive loops, clock and data recovery (CDR), and physical-layer calibration. * Partner with TPU Systems, Networking Software, and High-Performance Computing (HPC) teams to ensure silicon firmware integrates seamlessly with global cluster management and collective communication frameworks. * Identify and de-risk hardware-software interface bottlenecks (e.g., register maps, driver latencies, and boot-up sequencing) that impact Google's AI infrastructure. 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