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# ASIC SOC Methodology Design Engineer, AI Hardware

- **Company:** Tesla, Inc.
- **Location:** Austin, TX, United States
- **Experience:** Experienced
- **Contract:** Internship / Graduate position
- **Skills:** Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Electronic Design Automation, Static Timing Analysis, Tcl (Programming Language), Scripting, Application Specific Integrated Circuits, Build Tools, Hardware Acceleration, Physical Design
- **Published:** May 19, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=09a35b57a4d311de

## About the Role

* Degree in Electrical Engineering, Computer Engineering, or equivalent experience
 * 2+ years of industry experience (including internships) working with digital design EDA tools
 * Hands-on experience with one or more: Spyglass (CDC/lint/RDC), Conformal LEC, Formality, or equivalent
 * Understanding of clock domain crossings, reset synchronization, and synthesis fundamentals
 * Proficiency in TCL and/or Python scripting
 * Familiarity with SDC constraint development
 * Elementary understanding of DFx/DFT scan modes and their impact on CDC and constraints
 * Experience with both Synopsys and Cadence EDA tool ecosystems
 * Exposure to RTL filelist management and build systems at SOC scale
 * Experience with physical design flows (synthesis, PnR, timing analysis)

## Description

* Own RTL-to-PD integration and Spyglass lint sign-off flow, including filelist methodology, violation triage, and waiver creation
 * Set up, run, and maintain Spyglass CDC sign-off flows, configure DFx mode, triage violations, develop waivers, and drive fixes with design teams
 * Define and maintain RTL-to-SDC timing-constraint methodology across diverse IP blocks
 * Manage Spyglass RDC sign-off flows, perform reset-domain analysis, triage violations, develop waivers, and introduce robust reset scenarios with verification teams
 * Lead Conformal LEC formal equivalence checking (RTL-to-RTL, RTL-to-gate), debug failures, create constraints, and conduct sign-off reviews
 * Automate and enhance methodology flows using TCL and Python scripting
 * Collaborate with RTL design, DFT, timing, and physical design groups to scale methodologies across the full SOC


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