> Markdown version of [/jobs/ext/2592604-asic-design-verification-technical-lead-high-speed-dsp](https://www.wearedevelopers.com/jobs/ext/2592604-asic-design-verification-technical-lead-high-speed-dsp). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC Design Verification Technical Lead, High-Speed DSP - **Company:** Google LLC - **Location:** Sunnyvale, CA, United States - **Experience:** Expert - **Salary:** $240,000.0 - $333,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Computer Engineering, Software Debugging, Formal Verification, SystemVerilog, High Performance Computing, Application Specific Integrated Circuits - **Published:** August 9, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=dce3e55ea5f2fb83 ## About the Role * Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field. * 12 years of experience in design verification. * Experience in high-speed PHY layers, high-speed interface subsystems, or mixed-signal verification., * Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field. * Experience defining verification architectures, methodologies, and roadmaps for AI accelerators, High-Performance Computing or high-bandwidth networking silicon. * Experience bridging the gap between Pre-Silicon verification (simulation and emulation) and Post-Silicon validation and correlation. * Experience driving advanced verification methodologies. ## Description * Design, build, and scale constrained-random verification environments using SystemVerilog and UVM for high-speed physical-layer DSP blocks. * Build co-simulation frameworks and predictors to compare RTL implementation output against high-level algorithmic models. * Define and execute functional coverage plans, utilizing covergroups and SystemVerilog Assertions to verify architectural corner cases, fixed-point quantization effects, and numerical overflows. * Author dynamic stimulus sequences and virtual sequencers to stress-test adaptive feedback loops under realistic channel impairments, including noise, ISI, and high-frequency jitter profiles. * Lead the debugging of RTL and environment failures, collaborating closely with algorithm and DSP designers to isolate and resolve discrepancies between the RTL implementation and the specification. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form. ## Related Videos - [When testing just doesn’t cut it](https://www.wearedevelopers.com/videos/720-when-testing-just-doesn-t-cut-it) - [Using AI Without Losing Your Skills](https://www.wearedevelopers.com/videos/2045-using-ai-without-losing-your-skills) - [You don't need to write the code. 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