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# Sr FPGA Engineer II

- **Company:** Job Owl
- **Location:** Danbury, CT, United States
- **Experience:** Expert
- **Salary:** $140,000.0 - $180,000.0
- **Contract:** Permanent contract
- **Skills:** Cyber Security, Computer Engineering, Ethernet, Field-Programmable Gate Array (FPGA), Hardware Design, Performance Tuning, Scrum Methodology, SystemVerilog, Data Processing, Scripting, Information Technology, Code Inspection
- **Published:** August 12, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=05a3d213cd06ea21

## About the Role

* Education
 + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience. Master's degree is a plus.
 * Experience
 + 8+ years of FPGA and embedded systems experience.
 * Knowledge, Skills & Abilities
 + Expert knowledge scripting and coding (Experience with SystemVerilog[RT1] a plus)
 + Experience with advanced FPGA verification methodologies and Test Benching.
 + Expertise in simulation (Xcellium) and familiarity with linting programs (DVT)
 + Experience in Xilinx/AMD Versal and Ultrascale+ devices a plus
 + Strong understanding of AXI, HSS, Ethernet protocols
 + Strong understanding of embedded systems.
 + Strong leadership and troubleshooting skills.
 * Additional Competencies/Requirements
 + Candidates must be able to obtain/maintain a security clearance.

## Description

The Senior FPGA Engineer II leads the design and development of complex FPGA-based hardware systems and packet handling applications supporting advanced cybersecurity solutions. This role provides technical leadership for FPGA architecture, design, simulation, verification, integration, and optimization efforts while mentoring junior engineers and contributing to strategic engineering initiatives. The Owl hardware team is seeking motivated individuals with strong coding abilities to join our team in pursuit of cutting-edge designs and pushing the envelope of the possible., * Lead FPGA architecture and development activities.

 * Develop advanced FPGA data filtering mechanisms. This may include designs for high-speed applications or significant data modification.
 * Provide technical leadership for simulation and verification efforts.
 * Code verification and UVM test benching.
 * Support hardware integration and performance optimization.
 * Support Test plan and implementation.
 * Mentor junior engineering staff.
 * Participate in AGILE Scrum leadership activities.


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