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# CPU Sub-system Design Verification Engineer

- **Company:** Globalfoundries U.S. Inc.
- **Location:** Santa Clara, CA, United States
- **Salary:** $188,000.0 - $325,000.0
- **Contract:** Permanent contract
- **Skills:** C (Programming Language), Computer Engineering, Perl (Programming Language), Formal Verification, Field-Programmable Gate Array (FPGA), Python (Programming Language), Reduced Instruction Set Computing, Subsystems, SystemVerilog, Test Case, Scripting
- **Published:** May 14, 2026
- **Apply:** https://www.jofdav.com/jobs/58041027-cpu-sub-system-design-verification-engineer

## About the Role

* Bachelor's or Master's degree in Electronics/Electrical/Computer Engineering.
 * 15+ years of experience in design verification, preferably in CPU or SoC verification.
 * Hands-on experience with SystemVerilog, UVM, and constrained random verification.
 * Familiarity with CPU architectures such as RISC-V, ARM, or MIPS.
 * Basic understanding of cache and coherency concepts.
 * Strong scripting skills in Python, Perl, or Shell., * Exposure to RISC-V architecture.
 * Knowledge of interconnect protocols like AXI, ACE, or CHI.
 * Experience with FPGA prototyping or emulation platforms.

## Description

MIPS - A GlobalFoundries company is seeking a Design Verification Engineer with 15+ years of experience to join our CPU verification team. The successful candidate will work on verification of processor components, focusing on CPU core functionality, coherency, and cache subsystems. This role offers an excellent opportunity to contribute with advanced verification methodologies and collaborate with world-class architects and designers., * Perform functional verification of CPU cores and related subsystems (coherency and cache controllers).

 * Understand and interpret microarchitectural specifications to develop effective verification strategies.
 * Develop and execute verification plans, including testbench creation and test case development.
 * Write directed and constrained random test cases in SystemVerilog, C, and Assembly.
 * Utilize UVM-based environments for coverage-driven verification.
 * Analyze coverage reports and assist in closing coverage gaps.
 * Automate regression and verification flows using scripting languages such as Python, Perl, or Shell.
 * Collaborate with senior engineers and architects to ensure design quality and performance.

Other Responsibilities:

 * Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.


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