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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # TPU SoC Integration Engineer, Cloud - **Company:** Google LLC - **Location:** Sunnyvale, CA, United States - **Experience:** Expert - **Salary:** $163,000.0 - $236,000.0 - **Contract:** Permanent contract - **Skills:** Bioinformatics, Cloud Computing, Computer Engineering, Perl (Programming Language), Emulators, Python (Programming Language), Static Timing Analysis, System on a Chip, Tcl (Programming Language), Application Specific Integrated Circuits, Information Technology, Physical Design - **Published:** August 1, 2026 - **Apply:** https://www.techcareers.com/job.asp?id=3338249389&tx=JK5549FFL&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54 ## About the Role Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area., * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 8 years of experience in ASIC design or RTL design. * Experience with SoC design and integration. * Experience with multi-chiplet SoC integration. * Experience with SoC Design for Testing (DFT) planning. * Experience scripting in Python or Perl or Tcl., * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. * Experience with SoC signoff-Logic Equivalence Check (LEC)/Lint/Unified Power Format (UPF)/CDC/Reset Domain Crossing (RDC) flows. * Cross-functional experience with Design Verification (DV), Physical Design (PD), Clock Domain Crossing (CDC) and DFT teams. * Experience designing and constructing ASIC Input/Output (IO) pad-rings. * Knowledgeable in 3DIO methodology, voltage and clock domain partitioning. * Knowledgeable in ASIC top-level Static Timing Analysis (STA) and clock planning. ## Description * Lead advanced SoC integration projects from concept to final delivery, managing project milestones, deliverables, and cross-functional schedules. * Partner with ASIC teams on complex interposer and package design, and resolve multi-die physical design challenges leveraging 3DIO and domain partitioning expertise. * Utilize software-based construction to seamlessly integrate SoC IPs and maintain complete ownership of the upper-level RTL hierarchy up to the package level. * Collaborate closely with Verification and Emulation teams to resolve complex connectivity issues and optimize system compilation. * Participate in critical layout design decisions and SoC-level sign-off activities to ensure robust, high-performance silicon delivery. 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