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# SystemC Modeling Developer (Remote)

- **Company:** UST Inc
- **Location:** San Francisco, CA, United States (Remote available)
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Application Programming Interfaces (APIs), Artificial Intelligence, BIOS, C++ (Programming Language), Profiling, Computer Engineering, Software Debugging, Firmware, PCI Express, Quick EMUlator (QEMU), Software Engineering, SystemC, Performance Testing, Model Validation, Information Technology
- **Published:** August 2, 2026
- **Apply:** https://diversityjobs.com/main/sendform/8/8/28176/1/17801255?backUrl=%2Fcareer%2F17801255%2FSystemc-Modeling-Developer-Remote-California-San-Francisco

## About the Role

* Bachelors or Masters degree in Computer Engineering, Electrical Engineering, Computer Science, or related field.

 * 5+ years of experience in the following areas:

 * SystemC/TLM modeling, TLM2.0, and C/C++.

 * Computer architecture including CPU pipelines, cache hierarchy, memory controllers, PCIe/CXL, and AI/compute subsystems.

 * Pre-silicon simulation, or architectural modeling for semiconductor/server platforms.

 * Cycle-accurate, timing-accurate, or transaction-level modeling.

 * Pre-silicon simulation flows and virtual platform development.

 * Performance data, interpret system behavior, and provide optimization insights.

 * Debugging skills in complex simulation environments., Firmware Development, C++, ARM, BIOS, Debugging, Performance Testing, Performance Modeling, Hardware Architecture

## Description

UST is searching for a skilled SystemC Modeling Developer to join our Server Architecture & Performance Engineering team. In this role, you will design and develop SystemC/TLM models for next-generation Compute and AI server platforms, enabling architecture exploration, performance analysis, and pre-silicon software development. This is a high-impact opportunity to directly influence future server SOC and platform designs.

The opportunity:

 * Develop SystemC/TLM2.0-based functional, timing, and performance models for server subsystems (CPU, memory, I/O, accelerators, AI engines).

 * Build modular, scalable models for Compute & AI workloads and integrate them into simulation frameworks.

 * Perform system-level performance modeling, profiling, and bottleneck analysis across compute, memory, and accelerator paths.

 * Support pre-silicon BIOS, firmware, and driver enablement using virtual platforms.

 * Validate models against RTL or hardware references to ensure functionality and accuracy.

 * Work with simulators such as Synopsys Virtualizer, Cadence VSP, QEMU-based frameworks, etc.

 * Collaborate with architects, RTL designers, platform engineers, and performance teams to align modeling results with product goals.

 * Document model features, APIs, interfaces, and usage workflows for internal teams.

This position description identifies the responsibilities and tasks typically associated with the performance of the position. Other relevant essential functions may be required.


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