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# Network Interface Controller (NIC) Architect

- **Company:** Broadcom
- **Location:** San Jose, CA, United States
- **Salary:** $200,000.0 - $320,000.0
- **Contract:** Permanent contract
- **Skills:** Application Programming Interfaces (APIs), Network Congestion, Ethernet, Network Interface Controllers, Firmware, Field-Programmable Gate Array (FPGA), Software Architecture, Remote Direct Memory Access, Systems Architecture, Load Balancing, Application Specific Integrated Circuits, Data Pipelines
- **Published:** August 6, 2026
- **Apply:** https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-CA-San-Jose-Innovation-Drive/Network-Interface-Controller--NIC--Architect_R026772

## About the Role

* Education: MS or Ph.D. in Engineering, Computing, or a closely related discipline.
 * Experience: 16+ years of dedicated experience in high-performance Network Interface Controller (NIC) and network-system architecture.
 * Protocol Expertise: Deep understanding of RDMA transports, congestion control algorithms, dynamic connection management, and multipath packet spraying.
 * Hardware/Software Co-Design: Extensive background in FPGA/ASIC systems, direct memory access, and defining firmware/driver interfaces.
 * Leadership: Proven track record of cross-organizational decision-making and guiding hardware, software, firmware, and verification engineers through implementation.
 * Active participation or leadership in network standardization bodies (e.g., Ultra Ethernet Transport Software Working Group).
 * Experience defining composable hardware/software plug-in architectures or programmable packet-processing pipelines.
 * A strong portfolio of issued patents, academic publications, or technical reports related to network systems.

## Description

* Define end-to-end hardware/software architectures for Remote Direct Memory Access (RDMA), Ultra Ethernet, RDMA over Converged Ethernet (RoCE), and multipath transport.
 * Architect NIC datapaths, offloads, programmable congestion control, load balancing, and multiplane networking.
 * Translate customer, product, and standards requirements into implementable architectures using executable modeling, workload analysis, and silicon-aware tradeoffs.
 * Design and evaluate queue, buffer, and telemetry systems, ensuring memory architectures meet target workloads without requiring post-silicon corrections.
 * Interface with programmable logic team help define APIs and trade-offs between different solutions
 * Decompose collective-communication libraries (such as NCCL and RCCL) to derive minimum NIC primitives, feature dimensions, and hardware-software interfaces.
 * Act as a technical interface to strategic customers to help define solutions.
 * Drive multi-vendor convergence and standards development, participating in organizations like the Ultra Ethernet Consortium or Open Compute Project.
 * Influence product strategy, technical roadmaps, and cross-organizational engineering teams without direct management authority.


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