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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Digital Physical Implementation and Integration Engineer - **Company:** Micron Technology, Inc. - **Location:** San Jose, CA, United States - **Experience:** Expert - **Salary:** $145,000.0 - $246,000.0 - **Contract:** Permanent contract - **Skills:** Computer-Aided Design, Adobe InDesign, Artificial Intelligence, Analog Electronics, Computer Engineering, Software Debugging, Linux, Dynamic Random-Access Memory, Perl (Programming Language), Joint Test Action (IEEE Standards), Python (Programming Language), Static Timing Analysis, Tcl (Programming Language), Linux Virtual Server, Microsoft Power Automate, Git, Modeling and Simulation, Physical Verification, Physical Design, Cts+ - **Published:** August 14, 2026 - **Apply:** https://dejobs.org/x/x/1AD258A18F19478D8BB0884B43AEDED2/job/ ## About the Role * 5+ years of digital physical design with at least one full tapeout owned end-to-end. * Bachelor's degree in Computer Engineering or Electrical Engineering * Strong static timing analysis and debug skills. Fluent with PrimeTime across MMMC and OCV/AOCV/POCV; comfortable dissecting violations into clock, data, and derating contributors, and separating real issues from constraint or modeling artifacts. Experience with ILM / ETM block abstractions and ECO fixing. * Hands-on expertise with Cadence Innovus Hierarchical Flow or Synopsys ICC2 Design Planning - virtual flat, partitioning, pin optimization, budgeting, assembly. * Proven experience with top-level digital integration flow end-to-end - driving a full-chip or large-partition design from planning through assembly and hand-off. * Strong flat APR expertise with Innovus (or ICC2): floorplan, place, CTS, route, ECO, sign-off correlation. * Synthesis proficiency with Design Compiler or Genus (WLM + topographical/physical); comfort with size_only, don't_touch, MBFF, scan, clock gating. * Physical verification with Calibre: DRC, LVS, antenna, PERC; hierarchical vs. flat runs and waiver management. * SDC authoring for multi-mode/multi-corner designs; ability to derive and validate block budgets from top-level planning. * Fluent in Tcl and one of Python/Perl for flow automation. * Working proficiency with general-purpose agentic AI applied to engineering work - AI-powered assistants, MCP-based tool integration, and workflow automation. Candidates must be able to use and extend our internal AI toolkit from day one. * Solid grasp of CMOS logic , standard cells, RC extraction, EM/IR, and low-power techniques (MV, power gating, retention). * Linux/Unix, Git or similar VCS, Make-based flows. Preferred / Bonus: * Master's degree or Ph.D. in Computer Engineering or Electrical Engineering * Multi-partition SoC or memory top-level integration; experience driving ECOs across a hierarchy of 5+ blocks. * Clock planning at the top level - clock distribution across partitions, mesh/H-tree hybrids, boundary skew budgeting. Memory (NAND/DRAM) or mixed-signal design experience; comfort working alongside custom-layout and circuit designers. * Familiarity with DFT/scan compression, JTAG, MBIST and their interaction with partitioning. * Familiarity with EDA-vendor AI tools - Cadence Cerebrus / JedAI, Synopsys DSO.ai and copilots, or equivalent. * Contributions to methodology or CAD tooling (published or internal). ## Description * Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits * Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions * Leading all aspects of and managing the layout process including floor-planning, placement, and routing * Performing verification processes with modeling and simulation using industry standard simulators * Contributing to cross group communication to work towards standardization and group success * Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product * Proactively solicit mentorship from Standards, CAD, modeling, and verification groups to improve the design quality * Driving innovation into the future Memory generations within a dynamic work environment Design Planning & Top-Level Integratio * Perform top-level virtual flat placement to explore partitioning options and validate hierarchy quality before commit. * Implement top-level global routing to derive congestion, timing, and pin-feasibility signals that drive planning decisions. * Own partition creation : block shaping, abutment, channel/keep-out definition, and power-domain planning. * Drive pin optimization / pin cutting - pin placement, alignment, and count reduction guided by top-level routing. * Plan and implement repeater / feedthrough insertion : budget top-level nets, place repeaters, and manage crossings across partition boundaries. * Generate block-level constraints (timing budgets, boundary SDC, ILM/ETM models, physical constraints) directly from the design planning tool and hand them off to block owners. * Perform top-level assembly: integrate block-related work (LEF/DEF/GDS/ETM/ILM), close top-level timing, DRC, LVS, and EM/IR, and iterate ECOs to convergence. Block-Level APR * Implement full APR flow (init * floorplan * place * CTS * route * ECO * sign-off) on digital blocks; own block-level STA sign-off across corners alongside DRC, LVS, EM/IR, and antenna closure. * Set up new project and revision environments - collateral (SDC, netlist, LEF, QTM), stdlib migrations, and constraint authoring. * Debug and correlate synthesis vs. APR vs. STA (PPA regressions, DRV, size_only/don't_touch strategy, scan chain stitching). Methodology & Automation * Automate flows in Tcl / SKILL / Python; extend internal make-based flow and contribute to shared analysis tooling and dashboards. * Partner with STA, DFT, CAD, and custom-layout teams; document methodology and provide mentorship to engineers gaining experience. ## Related Videos - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [Docker exec without Docker](https://www.wearedevelopers.com/videos/1094-docker-exec-without-docker) - [Git for Code Reviews](https://www.wearedevelopers.com/videos/429-git-for-code-reviews) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Data Science & more: The Lopez dilemma](https://www.wearedevelopers.com/magazine/10-data-science-more-the-lopez-dilemma) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Best US AI Conferences for CTOs in 2026: Build vs. Buy, Vendor Evaluation, and Peer Intelligence](https://www.wearedevelopers.com/magazine/736-best-us-ai-conferences-for-ctos-in-2026-build-vs-buy-vendor-evaluation-and-peer-intelligence)