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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Sr. Principal SoC Power Management Architect - **Company:** Ampere Computing - **Location:** Portland, OR, United States - **Experience:** Expert - **Salary:** $225,500.0 - $356,000.0 - **Contract:** Permanent contract - **Skills:** ARM Architecture, Computer Engineering, Firmware, Data Driven Tests, PIC Microcontroller, Information Technology - **Published:** August 3, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=983fe8852f17b8b0 ## About the Role * 8+ years of proven, hands-on power architecture and SoC low-power expertise, including how architectural decisions map to DVFS/power-state control, power-state residency, and performance-per-watt trade-offs. * Deep HW development experience, from specification to integration of low-power features, with familiarity in RTL-level design and verification constraints. * Proven power optimization expertise, using measured results to improve SoC/IP power-saving effectiveness and validate net impact on performance and energy. * Expert knowledge of SoC low-power modes and IP low-power capabilities, covering power modes/states, wake-up/latency, and retention behavior. * Ownership of SoC-level low-power management flows, orchestrating subsystem entry/exit and power sequencing for robust behavior across corner cases and workloads. * Cross-functional leadership and communication, partnering with firmware/software/verification teams to ensure low-power architectural intent is delivered, validated, and maintained. * Additional skills highly desired: Familiar with SW/FW; Microcontrollers; HW/SW Co-Design; ARM Architecture; Power States, * BS degree in Electrical Engineering, Computer Engineering, or Computer Science & 12 years of related experience, MS degree & 8 years, or PhD & 5 years ## Description As a Sr. Principal SoC Power Management Architect, you will be responsible for driving SoC-level Power Management Architecture. You'll work with the business unit to understand the product requirements and drive SoC and IP-level specifications, partnering with product and cross-functional teams to deliver robust, data-driven solutions where power is a constrained resource. You will work with various SoC global and IP teams to drive capabilities needed to meet product power, performance and energy efficiency targets. What You'll Achieve: * Own end-to-end power management architecture, translating business power/performance goals into actionable SoC and IP requirements. * Drive SoC and subsystem power management architecture, partnering with the Product Power Management Architect to translate product requirements into implementable approaches. * Assess and expand IP power capabilities with subsystem architects-identify gaps and define new features using data-driven analysis. * Make HW/SW/FW trade-offs to deliver feasible, performant, and verifiable power management solutions. * Provide technical direction and architectural reviews leadership, with clear progression toward Lead Power Management Architect for the SoC and ownership of roadmap decisions and alignment. * Enable HW-SW codesign execution by partnering with senior architects and firmware developers to ensure integration matches architectural intent. * Provide technical direction to pre and post verification teams to deliver high quality work products (architecture definition, documentation, Si). ## Related Videos - [Unleashing the Full Potential of the Arm Architecture – Write Once, Deploy Anywhere](https://www.wearedevelopers.com/videos/940-unleashing-the-full-potential-of-the-arm-architecture-write-once-deploy-anywhere) - [User 1st! Technology 2nd! Stop building AI nobody uses - start delivering real business outcomes](https://www.wearedevelopers.com/videos/100337-user-1st-technology-2nd-stop-building-ai-nobody-uses-start-delivering-real-business-outcomes) - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [An Architect’s guide to reducing the carbon footprint of your applications](https://www.wearedevelopers.com/videos/559-an-architect-s-guide-to-reducing-the-carbon-footprint-of-your-applications) - [Passive ARM Assembly Skills for Debugging, Optimization (and Hacking)](https://www.wearedevelopers.com/videos/1083-passive-arm-assembly-skills-for-debugging-optimization-and-hacking) - [AI as a Test Designer: Transforming Experience into Automated Testing](https://www.wearedevelopers.com/videos/1984-ai-as-a-test-designer-transforming-experience-into-automated-testing) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [The Best X (Twitter) Accounts for Developers](https://www.wearedevelopers.com/magazine/294-the-best-x-twitter-accounts-for-developers) - [Data Science & more: The Lopez dilemma](https://www.wearedevelopers.com/magazine/10-data-science-more-the-lopez-dilemma) - [Why Event-Driven Architecture Isn’t About Speed (and When You Actually Need It)](https://www.wearedevelopers.com/magazine/745-why-event-driven-architecture-isn-t-about-speed-and-when-you-actually-need-it) - [How to Avoid Over-Engineering](https://www.wearedevelopers.com/magazine/546-how-to-avoid-over-engineering) - [Everything a Developer Needs to Know About MCP with Neo4j](https://www.wearedevelopers.com/magazine/604-everything-a-developer-needs-to-know-about-mcp-with-neo4j)