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# Security IP Design Engineer

- **Company:** ARM
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Salary:** $161,500.0 - $218,500.0
- **Contract:** Permanent contract
- **Skills:** Software Bug Management, Computer Engineering, Software Debugging, Perl (Programming Language), Firmware, Formal Verification, Python (Programming Language), Key Management, Oracle Virtual Machine, Static Timing Analysis, Subsystems, Systems Architecture, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Information Technology, U-Boot
- **Published:** August 5, 2026
- **Apply:** https://www.jofdav.com/jobs/59119137-security-ip-design-engineer

## About the Role

Preferred candidates will have successfully completed a Bachelor's or Graduate degree in Computer Science or Electrical/Computer Engineering. Successful applicants will have established track records of sophisticated ownership and leadership in the successful design and productization of Compute, Multimedia, or Security Sub-Systems and SoCs.

 * Advanced understanding of hardware Verilog RTL design, verification, and EDA methodologies.
 * Proven experience in Security Hardware, Embedded Processor Systems, Applied Cryptography, Secure Boot, Key Management, and Access Controls.
 * Proven experience in SoC architecture including multi-clock domains, AXI/AHB protocols, multi-power domains, and reset architectures.
 * Competency with synthesis, timing analysis, constraints development, and ECO methodologies.
 * Familiarity with design checks including CDC, RDC, X-Propagation, LINT.
 * Familiarity with power management techniques, UPF, power estimation, and power optimization.
 * Experience with Perl, Python, TCL, or other scripting language.
 * Familiarity with ARM-based designs and/or ARM System Architectures.
 * Experience with SystemVerilog and verification methodologies - UVM/OVM, Portable Stimulus, Hardware/Firmware co-verification.

## Description

As a creative and diligent Security Hardware Designer, you will be part of a team that will develop Security IP and Subsystems. You will develop architectures, specifications, and design sophisticated security hardware functions. We will partner with verification and implementation peers to build test plans, drive verification closure, support debug, and achieve functional, power, and performance sign off.

The Designer's primary responsibilities will include architecture specification, RTL and constraint development, bug fixing, and leading design exploration, optimization, and structural checks. You will contribute to the development and enhancement of processes and methodologies shared by the team. You will mentor team members and balance demands working with the leadership team on project management, roadmaps, initiatives, and schedules.


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