> Markdown version of [/jobs/ext/2642230-senior-principal-hardware-applications-engineer](https://www.wearedevelopers.com/jobs/ext/2642230-senior-principal-hardware-applications-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Principal Hardware Applications Engineer - **Company:** Bright Vision Technologies - **Location:** Santa Clara, CA, United States - **Experience:** Expert - **Salary:** $199,800.0 - $266,400.0 - **Contract:** Permanent contract - **Skills:** Computer Engineering, Hardware Design, Signal Integrity, AI Infrastructure, Network Switches, Hfss, Pcb Layout, Ansys, Hardware Debugging - **Published:** August 2, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=b6d0f689112bdd05 ## About the Role * Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field. * 15+ years of experience in high-speed hardware design, development, or validation. * 10+ years of hands-on Signal Integrity (SI) and Power Integrity (PI) experience with high-speed SerDes platforms. * Strong knowledge of 25G NRZ, 112G, and 224G PAM4 technologies. * Experience with SI/PI channel modeling, PCB layout, stack-up design, simulation, compliance testing, and SerDes tuning. * Strong understanding of PDN analysis, including impedance, IR drop, decoupling, transient response, and voltage droop. * Experience with SI/PI tools such as Ansys HFSS/SIwave, Cadence Sigrity/Clarity/PowerSI, or similar tools. * Hands-on experience with high-speed lab and test equipment, including VNAs, BERTs, oscilloscopes, TDRs, and jitter analyzers. * Strong customer-facing, technical leadership, communication, and problem-solving skills. * Experience providing technical guidance or training to engineering teams. ## Description * Lead SI/PI engineering activities for high-speed Ethernet switch and AI infrastructure platforms. * Define high-speed layout, routing, stack-up, and design guidelines for SerDes channels, power delivery networks, and sensitive interfaces. * Perform channel modeling, post-layout extraction, simulation, and analysis to identify and resolve design issues. * Conduct SI/PI design reviews and provide recommendations to improve performance and design margins. * Perform and review PDN simulations, including impedance, IR drop, decoupling, transient response, and voltage droop. * Support high-speed SerDes technologies, including 112G and 224G PAM4, and contribute to future 448G platform development. * Lead compliance testing, lab characterization, and hardware debugging using tools such as VNAs, BERTs, oscilloscopes, TDRs, and jitter analyzers. * Provide SerDes tuning and design guidance based on simulation results, lab measurements, and field data. * Work closely with customers, ODMs, silicon teams, hardware engineers, software teams, and operations teams. * Support reference design development, customer platform bring-up, qualification, and production ramp. * Develop and deliver SI/PI training for customers, ODM partners, and internal engineering teams. * Mentor engineers and provide technical leadership across strategic customer programs. * Contribute SI/PI expertise to future product architecture and technology roadmap discussions. * Travel to customer sites, ODM locations, and labs as needed. ## Related Videos - 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