> Markdown version of [/jobs/ext/2643028-sr-staff-soc-power-performance-architect](https://www.wearedevelopers.com/jobs/ext/2643028-sr-staff-soc-power-performance-architect). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Sr. Staff SoC Power & Performance Architect - **Company:** Ambiq Micro, Inc - **Location:** Austin, TX, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Application Programming Interfaces (APIs), Artificial Intelligence, Analysis of Variance (ANOVA), ARM Architecture, Confluence, JIRA, Collaborative Software, Computer Engineering, Cursor (Graphical User Interface Elements), Software Debugging, Dynamic Random-Access Memory, Field-Programmable Gate Array (FPGA), Python (Programming Language), Non-Volatile Memory, Software Architecture, Reduced Instruction Set Computing, Microsoft SharePoint, Tcl (Programming Language), Test Case, Git, Information Technology, Power Analysis (Cryptography), Physical Design - **Published:** August 24, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=7bfc642977f8db04 ## About the Role We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency., This role is ideal for a senior low-power SoC architect who enjoys hands-on analysis, silicon debug, architecture specification, automation, and customer-facing technical influence., * BS in Electrical Engineering, Computer Engineering, Computer Science, or related field. * 7+ years of architecture experience in low-power SoC, embedded SoC, semiconductor, MCU, processor, or related silicon environments. * Hands-on ownership of power and/or performance analysis, budgeting, and debug. * Experience with Cadence Genus or equivalent industry power analysis tooling. * Experience with power-aware simulation flows. * Strong Python and/or TCL scripting for modeling, automation, reporting, and analysis. * Demonstrated ability to write architecture and microarchitecture specifications that engineering teams can build from. * Strong written and verbal communication skills. * Ability to work effectively across hardware, software, physical design, validation, applications, field, marketing, and sales teams. * Experience with collaboration tools such as Confluence, SharePoint, JIRA, and Git., * MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field. * 10+ years of semiconductor or embedded SoC industry experience. * UPF / IEEE 1801 authoring or review experience. * Clocking/reset architecture experience. * Arm Cortex-M architecture experience. * Experience with Arm Cortex-A, RISC-V, DSP, or heterogeneous multicore architectures. * Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies. * Prior customer-facing, pre-sales, field, or applications engineering engagement. * Familiarity with AI-assisted engineering environments such as Claude Code, Cursor, or equivalent. Must be currently authorized to work in the United States for any employer. ## Description * Execute power and performance analysis across pre-silicon modeling, RTL power analysis, power-aware simulation, and post-silicon correlation. * Build and maintain SoC, subsystem, and use-case-level power budgets. * Drive variance analysis against power and performance targets, surfacing risks early. * Lead architectural debug of power anomalies in simulation, emulation, or silicon. * Trace issues from waveform to RTL to architectural intent to root cause. * Develop and automate power modeling infrastructure, reporting flows, regression dashboards, and analysis tooling using Python and/or TCL. * Characterize power states, transitions, leakage/dynamic splits, Vmin behavior, retention, and corner behavior on first silicon. * Feed silicon learnings back into next-generation architecture. * Contribute architecture and microarchitecture specifications for power management, clocking/reset, fabric, flow sequencing, software/hardware interaction, and power models. * Analyze process-node tradeoffs and translate them into architectural recommendations. * Support use-case and test-case development. * Partner with physical design on power domain partitioning and UPF/power intent mapping. * Work with software architecture teams to define power management flows, APIs, and power manager behavior. * Support FPGA teams during early bring-up of power management and global flows. * Translate silicon power/performance capabilities into datasheet guidance, competitive positioning, and customer-facing collateral. * Support pre-sales, field engineering, RFQ/RFI responses, customer meetings, and customer use-case power estimation as Ambiq's P&P subject-matter expert. ## Related Videos - [AIQSpecFlow: Improves and automates your agile process of specification and creation of testcases.](https://www.wearedevelopers.com/videos/100084-aiqspecflow-improves-and-automates-your-agile-process-of-specification-and-creation-of-testcases) - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [Improving quality with Agentic AI with Rovo Dev and Xray](https://www.wearedevelopers.com/videos/2005-improving-quality-with-agentic-ai-with-rovo-dev-and-xray) - [Unleashing the Full Potential of the Arm Architecture – Write Once, Deploy Anywhere](https://www.wearedevelopers.com/videos/940-unleashing-the-full-potential-of-the-arm-architecture-write-once-deploy-anywhere) - [Git for Code Reviews](https://www.wearedevelopers.com/videos/429-git-for-code-reviews) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) ## Related Articles - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Dev Digest 166: Sycophancy, Zip bombs and AI Native Development](https://www.wearedevelopers.com/magazine/585-dev-digest-166-sycophancy-zip-bombs-and-ai-native-development) - [Dev Digest 132 - Binging WADFlix?](https://www.wearedevelopers.com/magazine/473-dev-digest-132-binging-wadflix) - [A call for Guest Writers for the WeAreDevelopers Magazine](https://www.wearedevelopers.com/magazine/648-a-call-for-guest-writers-for-the-wearedevelopers-magazine)